Quote:
Originally Posted by Toni Wilen
I just tested. It works.
Unaligned RESET followed by JMP (A0) in next long word. Cache disable and flush followed by dozens of NOPs before RESET/JMP (A0) to guarantee flushed pipeline. (JMP instruction executing confirmed by testing with odd A0. It crashed.)
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Sh*t. I just re-checked the HRM example and the RESET instruction is actually unaligned. (Because it's preceded by a lea.l 2,a0.) Sorry. I just don't exactly how prefetch works in exact detail.
This has to be the most confusing section in the entire book, not least because of calling a normal soft reset a "Cold Reboot".
The 'why' question remains interesting. It seems to be the jmp (a0) instruction that should be aligned. Could it fail to prefetch jmp (a0) under some circumstances? That section only mentions as reason that the RAM will disappear when the reset instruction is executed. Could DMA interfere? The example doesn't turn off DMA. Could it be required from an early A1000 hardware bug?
I'll change my code to follow HRM of course, so maybe it's best pursued in a dedicated thread. Annoying as hell
Quote:
Originally Posted by ross
clr.l $2a(a6)
EDIT: but if execbase is destroyed there is no need to clear it..
I explicitly used st 7.w because in any ROM there is a check for an odd execbase address (which of course cannot be accepted),
so not even by chance you'll being able to execute something or pass checksum checks. |
I'm not sure what a/b meant, maybe something like
1. Your code destroys (actually not, asks ROM to later destroy) Exec and resets
2. Reset invokes ColdCapture()
3. ROM notices Exec is bad and rebuilds it, clearing ColdCapture()
...and that because of 2, if ColdCapture() has virus code it could be prepared and nonetheless "re-inject itself"/restore Exec values it saved when first injecting itself? Then Exec wouldn't be rebuilt.