Quote:
Originally Posted by Thomas Richter
No, and no again. Once again: MOVE16 bursts always, even on non-cachable data, even on data that goes over the Zorro bus. Which means that there need to be logic on the board that disables bursting to go through Zorro. Which may or may not be the case - you cannot in general assume that the hardware fixes a software configuration issue for you.
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Yes and yes again! You still have not realized that the Motorola/Freescale Errata and addendum info also applies to documentation errors (not just CPU mask set bugs). Unfortunately, the M68K programmers reference manual error was not corrected so I will correct it now.
ERROR (M68K PRM):
"Line transfers are performed using burst reads and writes, which begin with the long word pointed to by the effective address of the source and destination, respectively. An address register used in the post increment addressing mode is incremented by 16 after the transfer."
CORRECTION:
"Line transfers are
optionally performed using burst reads and writes, which begin with the long word pointed to by the effective address of the source and destination, respectively. An address register used in the post increment addressing mode is incremented by 16 after the transfer."
REFERENCE (M68040 Users Manual):
"5.4.6
Transfer Burst Inhibit (TBI)
This input signal indicates to the processor that the accessed device cannot support burst mode accesses and that the requested line transfer should be divided into individual longword transfers. Asserting TBI with TA terminates the first data transfer of a line access, which causes the processor to terminate the burst and access the remaining data for the line as three successive long-word transfers. During alternate bus master accesses, the M68040 samples the TBI to detect completion of each bus transfer."
BTW, my trusty Commodore A3640 has
never run a burst cycle since burst is permanently disabled on this card.