Quote:
Originally Posted by Mathesar
Naah, too easy  But probably even better than this:
https://www.google.com/url?sa=t&rct=...dpoEG39CRzHNY0
This is an old school (period correct) PLL in a DIP package that can run up to 16Mhz or so. But, if you let it run at just 7MHz and use the XOR-type phasedetector, the output of the phasedetector will be a nicely doubled 14MHz clock. |
If you are going to tinker with this, take care with the Kicad schematic. I think VMA (pin 19 of old 68000 socket) is driven wrongly. It should come out of a 74LS157 mux. IMO I would dump the 157s altogether and just put 5 jumpers, low-tech and smaller
Does your clock idea cater for 21MHz for later?
