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As far as I know code scheduling makes sense for the 68060 only. But I think that rearranging code is nothing an assembler should do.
This step is usually done by a separate scheduler program, which reads the source and parses all instructions for their register- and instruction-unit usage and latency. Then it outputs a source with rearragned instruction lines.
vbcc has such a portable instruction scheduler (vsc.c), but currently only support for 603/604 PowerPC exists. It also depends on the compiler inserting "#barrier" or ";barrier" comments into the source, to define the barriers which should not be crossed by rearrangements. Otherwise it would be much too difficult to analyze the program flow.
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