Quote:
Originally Posted by phx
To be honest, I'm probably too tired to see the race condition.  |
The same here, but maybe because I still have not got a nice strong espresso.
EDIT: no effect from coffee
Quote:
The old solution with two INTREQ-writes after BLTSIZE even looks more dangerous to me, because a very fast blit could be finished before you cleared its IRQ flag for the second time. 
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And not only this.. an IRQ with high level can occur immediately after the blitter start and disrupt future chain
(the blitter, meanwhile, could finish before the INTREQ cleanup and lost a loop).
EDIT: lol, before the coffee I had not even seen that ohth313 written the same
This can be a solution:
Code:
move.w #$4000,intena(a6) ; Disable
move.w (a0),bltsize(a6) ; Start blitter
move.w #$40,intreq(a6) ; Acknowledge interrupt
move.w #$c000,intena(a6) ; re-Enable and double bus access
<pop stack here>
rte
Anyway the speech is worth if BLTPRI=0 (and a decent sized blit
), otherwise what phx wrote could happen even in this situation
(but from what I remember you do not set it at 1 if you can).
EDIT2:
It would be interesting to check if for a single word blit (with BLTPRI=0, considering the prefetch of the blitter and the relative delayed destination write in memory) the BLIT INTREQ bit is set before or after the CPU cleaning in a slow machine (like on A500).