Ok, got some time now to comment my code.
With a superficial look you can ask: "is not your code also cpu dependent?"
Response: "no, or better only relatively!"
This code is internal BUS timing dependent because even if you ignore all instructions on main wait cycle, I give to my routine a minimum time to last.
EDIT: before giving up and thrown an error it takes a lot of time on A500 (~2.7s), on fast cached 030+ practically the time explained later.
Some math (taking PAL Amiga as reference but the concept is the same on NTSC):
- internal BUS timing is 3546895Hz (C2 clock), but the processor can access only the even cycles, so an INTENAR read require a fixed (1/C2*2)=~564ns time
- a floppy revolution require ~200ms, but this is not a valid time because there is more to consider
(how many bits are really required by the game throught DMA, how many parts (sectors) there is on track, how big is the gap)
- disassembling we've a DMA request of $19CE words and 10 sectors/track (512 bytes/sector), so continue with math
- $19CE words require ($19ce*16*2ns)=~211ms (time the DMA require to read from disk after the sync is found)
- then there are two possible malus:
1) start reading immediately after the sync so you need a whole sector (1/10 track, ~20ms) before the next sync;
2) start reading at the gap start that can be bigger as $19CE-(512*10)-syncs-headers=~$5B0->~47ms;
- take the worst value of the two and sum to reading time ~(211+47)=258ms
- finally, how many CPU bus cycles there is in this time? (0.258s/564ns)=~457550->$6fb1c->
$70000
Now you can get where my [
moveq #7,d0
,
swap d0
] comes from and you can understand why this routine is not casual and require a bit of Amiga consciousness to be made
(at least for an online patched version)
Cheers!
PS: not that I would use such a technique, in fact in my loader I use the CIA timers, but for a dirty patch it can also be fine