Quote:
Originally Posted by litwr
Intel's oddities have explanations but Moto's are often just postulated.
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Explanations ? I'd like to know them ! Tell me why you don't get the overflow bit (OF flag) with LAHF/SAHF instructions, for example ? Or why SHL and SAL instructions are exactly the same ?
And i'm not speaking about encoding oddities !
Moto's are not postulated, they're easy to understand when having coded enough on it. Just ask me if you want to know more
Yet some things on x86 are just plain stupid, like that "DF" bit in the flags, making instructions behave in a different way depending on it, and, of course, making the auto-decrement inconsistent with that of the stack.
On 68k the code always disassembles the same way, on x86 you now have 3 modes with incompatible code.
Quote:
Originally Posted by litwr
Why? It is was very clumsy with 80286 but all use paged mode since 80386 which is still the best known.
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Well, i know full well what happens on 68k when you go to supervisor mode.
I have read many manuals and still have no clue of what happens when you change the privilege level on x86. Perhaps you could explain - should be easy if it's "best known".
Quote:
Originally Posted by litwr
There is BSWAP and fast shift and rotate instructions for these cases.
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Nevertheless this AH,BH,CH,DH stuff is an oddity. It's old remnant from 16-bit times.
Quote:
Originally Posted by litwr
It is quite regular since 80386.
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It didn't change in 80386, new things just got added.
So we even have two very different ways to interpret an addressing mode now - worse than before.
Anyway, no dep[sp], no [bp] mode, strange SIB byte in encoding - not what i'd call regular.
Quote:
Originally Posted by litwr
These registers were the best way for a 16-bit processor to work with 1 MB memory. When GP registers became 32-bit then the segment registers became obsolete. x86_64 doesn't use it at all. Moto's address registers are just more advanced analogue for Intel's segment registers. However Intel's ISA allows to forget them, they do not require bits in the instructions.  |
Yet they remain an oddity and i doubt it was the best way to overcome the addressing limitations...
Quote:
Originally Posted by litwr
I agree that 8 semi-registers are better than no registers at all. However the price is high. They have polluted Moto's ISA by clumsy instructions like ADDA, MOVEA, ... IMHO it would be better if ADDA, SUBA, ... worked as the normal instructions and set flags.
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Assuredly, no. MOVEA, ADDA, SUBA, CMPA, are not pollution. It's not a price we pay, it's a benefit : they offer sign extend for free and provide a way to perform some operations without touching the flags - both are useful. Actually i'd even like to have more of them...
Quote:
Originally Posted by litwr
How did x86 work with one stack? If an interrupt occurs then an application can't use any stack. So an interrupt may use a stack of any program. This may create a problem if a program uses a very little stack but this maybe regulated by system requirements to the user applications. |
Yes it can work, but having two stacks is a lot more practical - and a lot safer.
And anyway user programs don't need to care about this.
Quote:
Originally Posted by litwr
Intel ISA uses interrupt gates in the protected mode this gives much more than an additional stack.
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Yeah it gives a whole mess
Can you tell me what are the exact operations that are taken when an interrupt comes in protected mode ?
Quote:
Originally Posted by litwr
x86's auxiliary carry is for obsolete BCD instructions. IMHO it is a shame that these stupid instructions wasted ISA of x86, 680x0 or even 6502. However x86_64 is free of this shame.
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Back in the old day, they made sense. BCD was much more common than today.
Quote:
Originally Posted by litwr
The overflow flag is essential for work with the signed arithmetic, for example, GT or LE conditions.
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That wasn't the question ! The question is why is it not available by lahf/sahf while all other common flags are ?
Quote:
Originally Posted by litwr
The parity flag is required rarely but sometimes it is useful. BTW I used it even with z80. It gives information about a byte. |
I'd like to see a really useful example of this.
Quote:
Originally Posted by litwr
Spartans were not weak. They were the great warriors.
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But they didn't exactly lived an enjoyable life...
And a spartan cpu
is weak. Because it doesn't provide the tools to do the job so many instructions have to be used in place of one.