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Old 18 August 2016, 20:46   #79
meynaf
son of 68k
 
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Join Date: Nov 2007
Location: Lyon / France
Age: 51
Posts: 5,351
Quote:
Originally Posted by matthey View Post
Is a <150MHz FPGA processor a modern processor?
In some way, yes.


Quote:
Originally Posted by matthey View Post
It would be helpful to see some timed results of a variety of code executing with no dynamic prediction and with a hybrid 2 bit saturating with hint bit but everyone has already decided what is "useful".
You know full well what these results would say. Comparing 2 bit saturating with and without the hint bit, is quite easy : at best a few clocks for the two first iterations (if the hint bit isn't simply completely off, a likely situation for compiled code), and then nothing at all. Optimizing is about the needs of the many - not the needs of the few.


Quote:
Originally Posted by matthey View Post
The cost of a hint bit on the 68k is so high that it is practically free but lets reject it as not "useful" even though most research shows a branch prediction improvement for practically free.
Special cases in encoding, assemblers and disassemblers, aren't what i call "practically free". Don't play your gunnar, there are costs aside of the implementation.


Quote:
Originally Posted by matthey View Post
This is not a problem for real code. Why not blame the 68k ISA creators for making useless encodings too?
Useless encodings come from the fact special cases are costly to handle in comparison to the small benefit, no more no less. But this is not the point. I will always be against frankenstein-like stuff that's added for the mere sake of 'speed'.


Quote:
Originally Posted by matthey View Post
I documented the least significant bit of the displacement as reserved for these instructions. The CPU handles these different than Bcc even if the encoding is similar.
Here the whole Bcc area is split between two cases. How they are handled internal to the cpu, is irrelevant.


Quote:
Originally Posted by matthey View Post
The CPU decodes into a 32 bit displacement as quickly as possible. The 68060 does not have a cycle penalty for a Bcc.W or Bcc.L so this does not appear to be a problem. The hint bit would be available at the same time as the displacement.
The displacement is useless if the branch is "not taken". Unsure this fact is usable or not, nevertheless i wouldn't risk this for a hint bit.


Quote:
Originally Posted by matthey View Post
I wish to reduce my time spent posting here. I do not view this thread as productive and the ISA is dead end anyway. It only has historical significance as these were the ideas which the "Apollo non-Team" came up with and were discarded with minimal evaluation before a 68k+MMX bolt-on was decided by Gunnar. RIP 68k.
So long then, it has been fun
The 68k remains the best existing ISA, even if you consider it dead.
Gunnar has changed his mind when facing the gruesome facts for the emulation library and it seems current version does not have this silly c2p/pixmerge stuff he once wanted to add (and not even additional data registers). He is likely to change again when seeing the uselessness of what he has added.
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