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Originally Posted by meynaf
Is this puzzle/paradox solved now ?
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I enjoy the journey, not the destination!
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PC doesn't have its low bit wired to zero. If you do a jump or a branch to an odd address, then you'll get an address error. Same if an RTS pops an odd value. These are the only causes of address errors on 020+, btw.
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Yes this is correct, but is it the attempt to set bit zero that causes the error, or the attempt to actually execute from it? Because it certainly doesn't stay set for very long, as soon as the exception handler takes over it's back to an even address again. Unless the trap vector is also pointing to an odd address, in which case i don't know what happens...
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Bugs causing jumps to bogus addresses, which end up into data such as text, with all these 6x codes, is a common cause for 80000003 errors.
I've already warned about the use of this bit, which would break any program using an odd address branch to deliberately trigger an exception.
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Yes, quite, but i did also ask, should we really be pandering to this sort of code?
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For a byte address, absolutely none. For a byte offset, a bit more. For byte data, a lot.
Remember that i am for more data uses for An registers - as i'm quite often out of data regs, but more rarely of address regs. I've even used address regs to represent R,G,B values 
If you don't like the data/address register split, you should understand the use for this quite easily.
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It is a noble goal for sure, and were i to design an ISA from scratch to be source-code compatible with 68k i would certainly try to avoid the register split, but working around existing 68k encodings to achieve this can get a bit messy.
Just consider for instance, LEA d8(An,Rn),An...
Now the Rn can be a An or a Dn, and the bit that selects it can be considered the high bit in a four-bit register field. So far so good. So what about LEA to Dn? There, the A/D bit has to be on the other side of the register... in other words it still looks like a 4 bit register field but with the bits in a different order.
And that's before you get onto the possibility of "Data register indirect" addressing modes, for which there is just not enough encoding space.
Anyway it certainly involves "special cases" to handle unsigned byte offsets/data. Short branches use signed byte offsets, as do the d8(An,Rn) addressing modes mentioned earlier, and even the venerable moveq.l #n,Dn sign extends its byte data.
EDIT: also of course we already have the "special case" of the stack pointer (A7), which increments and decrements by 2 instead of the usual 1 using (A7)+/-(A7) on byte sized operations.