FrenchShark

Hello,

this is a cross-post from A.org.

It is a little bit OT but, it can be interesting for Minimig owners.
I have ported the coin-op game from Capcom to an FPGA.
Check this little video:
http://www.youtube.com/watch?v=9UuDf9zZqCg

The game fits in 3500 LEs (I did not write the sound part yet).
It is displayed on a VGA screen at 1280x1024, 60Hz.
The internal architecture is built on 16-bit bus running at 24 MHz (384 clocks per scanline, 1048 lines per frame) with a 8-channel DMA scheduler :
- the main Z80
- the audio Z80 (not used yet)
- the scroll #1 tilemap
- the scroll #2 tilemap
- the scroll #1 graphics
- the scroll #2 graphics
- the sprite graphics
- the character graphics
All the game ROMs (864KB) are stored in an external SSRAM and are accessed through DMA.

If the Minimig HW is fitted with 10ns SRAM, it is possible to run this game.

Regards,

Frederic

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Dimlow

This looks good, are you running it on Altera Dev board and if so what one.

X-ray

That was one of my favourite arcade games, especially two player co-op

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FrenchShark

No, it is a custom board I have made at work.
But, any dev board with at least 1 MB of fast SRAM can run it.
The Minimig has slow SRAM (55 ns), at least 20 ns SRAM has to be fitted to make it compatible with this game.
Now, I am working on putting the Scale2X algorithm in the game to improve the gfx quality. Then, I will had the sound

Regards,

Frederic

Dimlow

I wish there was a way i could just suck up all this FPGA knowledge that that you guys have. My learning seems to be going so slow. All i have managed to do so far is flash a few leds on the dev board.

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FrenchShark

In my case, I have learned VHDL at school 12 years ago, it was for ASIC design.
Then, in 2004-2005, with the C-One phenomena, my interest for VHDL came back. At the same time, the dev boards started becoming affordable. I was able to get two boards at work for some serious projects.
1943 is the first "fun" project I have made.
I recommend the website fpga4fun to start with FPGA.
The hard part with VHDL is the sequential logic with state machines and pipelines.
Some recommendation for the VHDL processes :
- Your first IF should be the asynchronous reset condition with the power-up init for the registers : IF (reset = '1') THEN
- Then, you have a : ELSIF rising_edge(clock) THEN
- Every assignment after the THEN is synchronous with the clock.
- Here, you can have additional IF conditions : they will be translated to clock enable, count enable, synchronous clear or set to registers or counters.
- You can also use CASE() .. WHEN => when you want to create a state machine.

Regards,

Frederic

gklinger

What is the value of the hardware you're using?

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FrenchShark

around $250 - $300.
The most expensive part is the 8MB SSRAM ($130 !!).

Regards,

Frederic

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FrenchShark

A little update :
I have fixed the aspect ratio of the game.
Now it looks like the original.
The bus clock is at 24 MHz and the dot clock at 64 MHz.
The clock domain crossing is done through 5 FIFOs (one per layer).
I do quad buffering on the FIFOs in preparation of the scale2x algorithm.
I will post a new video, once the scale2x is fully functional.
Now, it is time to go to bed

Frederic

FrenchShark

I have put a new video on youtube showing the correct aspect ratio and the scale2x algorithm :
http://www.youtube.com/watch?v=c39E5lhOPTM
Unfortunately, the video quality on youtube sucks so you cannot really see the improvement of the Scale2X.
Now I am looking at the YM2203, FM synthesis is harder than what I though .

Regards,

Frederic

Dimlow

It may look better if it was rotated by 90 deg, then it would fit the screen.

As for the Audio will this help http://passionoric.ifrance.com/fr/project/hsound.htm

There is some VHDL source for the AY-3-891x , i believe this is a compatible chip to the YM2202

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Dimlow

Did you ever get the audio to work ?

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keyway

I also want to play game?...