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Old 26 January 2018, 02:50   #1
AwoLStill
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An SPI Interface thread...

All this talk of TerribleFire, TF520, TF530, TF534 and Kipper2k K1208 with SPI port set me thinking, perhaps we should have a thread listing what things are available that might be compatible, to "sew a seed" in the imagination of others.

This is what I've found so far - all under £10 each, delivered:

Micro SD Storage Board TF Card Reader Memory Shield Module SPI for Arduino
https://www.ebay.co.uk/itm/161894497761

BMA180 digital Triple Axis Accelerometer Breakout SPI I2C Interface Module
https://www.ebay.co.uk/itm/142645659946

ENC28J60 Ethernet LAN Network Module with SPI Communication
https://www.ebay.co.uk/itm/263440790135

(Alternative)
Ethernet Network Modules W5500 TCP/IP 51/STM32 SPI Interface For Arduino new
https://www.ebay.co.uk/itm/142509342969

(Alternative-alternative)
USR-ES1 ENC28J60 W5500 Chip SPI to LAN/ Ethernet Converter TCP/IP Module New
https://www.ebay.co.uk/itm/142251960705

CH375B U-DISK Read Write Module USB interface communication SPI interface
http://www.ebay.co.uk/itm/182575858329

Serial:UART/I2C/SPI Adapter+1602 Yellow/Green LCD for Arduino/AVR/PIC
http://www.ebay.co.uk/itm/252417049379

AHRS Module Compass Modules Sensor Tilt-compensated Serial SPI Interface BEST
https://www.ebay.co.uk/itm/142031044835

This is some cool stuff that happens to be cheap!

Have you seen any cool SPI devices you'd like to hook up to an Amiga?

Related Threads:

Terrible Fire Accelerators
http://eab.abime.net/showthread.php?t=85380

K1208 8mb Fastmem board for the A1200
http://eab.abime.net/showthread.php?t=89568

Last edited by AwoLStill; 26 January 2018 at 03:03.
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Old 26 January 2018, 11:20   #2
E-Penguin
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Servos. Lots of servos. Replace your gotek with a stack of floppies and a robot arm.

https://www.adafruit.com/product/1429
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Old 26 January 2018, 13:50   #3
solidcore
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Lots of spi devices here . I would like to join forces with someone in getting Ethernet working as an Amiga driver to a common and widely used tcp stack on workbench 3.1 to amiga os 3.9. Pm me if interested .
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Old 26 January 2018, 16:57   #4
alexh
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How many free gates do these designs have in their CPLD/FPGAs?

Ideally a DMA capable design would be the best. I guess a PIO design to start with? Who has implemented the SPI core? Are they little more than GPIO?

To get good speed on SPI designs you have to support multi-bit parts which have more than 1-bit for their data interface.
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Old 26 January 2018, 20:44   #5
plasmab
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I am going to do all my SPI stuff on the TerribleFire accelerators thread. Not here.
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Old 26 January 2018, 21:45   #6
AwoLStill
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Quote:
Originally Posted by solidcore View Post
Lots of spi devices here . I would like to join forces with someone in getting Ethernet working as an Amiga driver to a common and widely used tcp stack on workbench 3.1 to amiga os 3.9. Pm me if interested .
I am! I can't guarantee I can code anything, but I'll happily try
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Old 26 January 2018, 21:45   #7
AwoLStill
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Quote:
Originally Posted by plasmab View Post
I am going to do all my SPI stuff on the TerribleFire accelerators thread. Not here.
Understood - hence me linking to it - you have enough to concentrate on!

:-)
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Old 26 January 2018, 21:47   #8
AwoLStill
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Wikipedia has this to say about SPI - we may need to pay close attention:

"The SPI bus is a de facto standard. However, the lack of a formal standard is reflected in a wide variety of protocol options. Different word sizes are common. Every device defines its own protocol, including whether it supports commands at all. Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low. Some protocols send the least significant bit first.

Some devices even have minor variances from the CPOL/CPHA modes described above. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the chip select line.

Some devices require an additional flow control signal from slave to master, indicating when data is ready. This leads to a 5-wire protocol instead of the usual 4. Such a ready or enable signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI masters do not support that signal directly, and instead rely on fixed delays.)

Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the JTAG or SGPIO protocols, or any other protocol that requires messages that are not multiples of 8 bits.

There are also hardware-level differences. Some chips combine MOSI and MISO into a single data line (SI/SO); this is sometimes called 'three-wire' signaling (in contrast to normal 'four-wire' SPI). Another variation of SPI removes the chip select line, managing protocol state machine entry/exit using other methods. Anyone needing an external connector for SPI defines their own: UEXT, JTAG connector, Secure Digital card socket, etc. Signal levels depend entirely on the chips involved."

Source:
https://en.wikipedia.org/wiki/Serial..._Interface_Bus
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