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Old 13 November 2017, 15:45   #1
mark_k
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Reiter Software Wedge

The Reiter Software Wedge is another simple board which allows an IBM PC MFM/RLL HD controller to be connected to the Amiga.

Should be pretty simple to add support for that. It's supposed to work with DTC-5150/5160 controllers, but from looking at the driver it seems to assume OMTI-like accesses. (Which don't really match the DTC-5150 manual on bitsavers.org...)

Non-AutoConfig, non-autoboot, no interrupts or DMA. PC I/O space appears at $EAxxxx. (It's possible the Wedge board could be jumpered to appear at a different address range, but the driver is hard-coded for $EAxxxx.)

The OMTI/DTC/whatever PC controller responds to I/O accesses at $320/1/2/3, which correspond to Amiga byte addresses $EA0641/3/5/7.

Driver/software disk and disassembly:
Code:
http://www.l8r.net/install/other/stuff/WEDGECARD_SYS.dms
https://www.media!fire.com/file/yiygs4l0e9sgovp/billsdisk_disasm_20171113.tar.gz
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Old 15 November 2017, 22:08   #2
Toni Wilen
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Sounds very boring (hardwired board without any intelligence..) so this is not going to be instantly implemented
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Old 15 November 2017, 23:42   #3
mark_k
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Possibly more "interesting" is that the buff and fmt programs on the software disk use some OMTI/DTC controller commands which other drivers don't. You need to correctly emulate $0E READ DATA FROM SECTOR BUFFER, $0F WRITE DATA TO SECTOR BUFFER, maybe $04 FORMAT DRIVE and $06 FORMAT TRACK (if the fmt program depends on what data is written by those commands; it seems to use WRITE DATA TO SECTOR BUFFER before issuing a FORMAT command).
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Old 16 November 2017, 20:05   #4
Toni Wilen
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Emulation added.

Format (It would have been nice to have quick instructions included..) does WRITE SECTOR BUFFER, fills it with repeating 0xb6 0xd9 pattern. Then it executes FORMAT TRACK (which returns success code) and hangs. So does FORMAT TRACK request data bytes if some unknown flag in last byte of command is set?

Command is: 06.00.00.00.04.85
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Old 16 November 2017, 22:01   #5
mark_k
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fmt and buff disassemblies:
Code:
https://www.media!fire.com/file/00ol58dfiflr8dp/fmt_buff_disasm20171116.tar.gz
FORMAT DRIVE (opcode $04):
OMTI manual says: "If bit 6 of the control byte is cleared, all the data fields are written with "6C". If bit 6 of the control byte is set, all the data fields are written with whatever data is in the data buffer."
FORMAT TRACK (opcode $06): Same meaning of that bit as for FORMAT DRIVE.

The OMTI manual describes format of control byte (CDB[5]) on page 6-2.

However, buf and fmt don't set bit 6 of the control byte. (They set bit 7 which tells the controller not to automatically retry.) They definitely seem to be expecting/assuming that FORMAT DRIVE/TRACK will use the data in the sector buffer. Maybe the DTC-5150/5160 board (which must have had OMTI-like firmware) did always work that way???

Also, the overall operation of the OMTI(/DTC-5150) controller is very close to the IBM Fixed Disk Adapter, maybe intended to be compatible with it? See pages 298 and on in Technical_Reference_Options_and_Adapters_Volume_2_Apr84.pdf.


Regarding the hang, the fmt code seems to expect status register bits 0-3 and 5 to all be set when the command completes. This from the end of the IssueFormatDrive routine:
Code:
	PEA	(OtherFormatDriveCDB0-DT,A4)
	JSR	(SendCDB,PC)
	ADDQ.W	#4,SP

.WaitCmdComplete
	JSR	(ReadStatusRegister,PC)
	MOVE.B	(StatusRegValue-DT,A4),D0
	EXT.W	D0
	EXT.L	D0
	AND.L	#$2F,D0
	CMP.L	#$2F,D0
	BNE.B	.WaitCmdComplete

	PEA	(1000).W
	JSR	(DelayLoop,PC)
	ADDQ.W	#4,SP

	MOVEA.L	(_EA0641-DT,A4),A0
	MOVE.B	(A0),(StatusByte-DT,A4)
	BTST	#1,(StatusByte-DT,A4)
	BEQ.B	.Done

	PEA	(Errorcouldnot.MSG1,PC)
	JSR	(_printf,PC)
	ADDQ.W	#4,SP

.Done
	UNLK	A5
	RTS

Errorcouldnot.MSG0	db	'Error - could not fill sector buffer',$A,0
Patienceforma.MSG	db	'Patience, formatting drive... ',0
Errorcouldnot.MSG1	db	'Error - could not format',$A,0
So on command complete, it expects:
IREQ = 1 (command complete) [bit 5]
BSY = 1 (controller selected) [bit 3]
C/D = 1 (byte being transferred is command or status) [bit 2]
I/O = 1 (direction of transfer is from controller to host) [bit 1]
REQ = 1 (request transfer of one byte via data in or data out) [bit 0]

Last edited by mark_k; 16 November 2017 at 22:09.
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Old 16 November 2017, 23:25   #6
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By the way, you should be able to enable debug mode in the fmt program which prints some logging/diagnostics.

Using a binary file editor, change byte at offset $4DC1 from $00 to $01. (See DebugFlag, offset $4D76 in the ReSource disassembly.)
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Old 17 November 2017, 20:46   #7
Toni Wilen
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OMTI emulation didn't work like spec says (OMTI 5510 Winchester Controller Jun85), reading STATUS cleared interrupt, not when DATA was read. I changed it to clear when status phase DATA was read but it caused driver to hang after it has read the "superblock". (Format seems to require opposite behavior..)

Code:
lbC000A9E
	MOVE.B	(A4),D0 ;Read DATA IN status byte (spec says this should clear IREQ and other status bits)
	BTST	#1,D0 ; ERROR bit set?
	BNE.W	lbC000B60

	MOVEA.L	#SectorBuf,A0
	MOVE.L	(A0),D0
	CMPI.L	#'WEDG',D0 ; "superblock"?
	BNE.W	lbC000B60

<snip>

lbC000B60
	MOVE.L	#$FFFFFF,D1
lbC000B66
	MOVE.B	(A2),D0 ;Read STATUS
	ANDI.B	#$3F,D0
	CMPI.B	#$20,D0 ;IREQ set? But IREQ should be clear now!
	BEQ.W	lbC000B7E

	SUBQ.L	#1,D1
	BNE.B	lbC000B66
"When the STATUS byte is read from the DATA IN register, the controller clears the IREQ and IRQ5 (If enabled), clears C/D, I/O, and BSY bits in the STATUS Registers, and enters the idle state"

Or did IBM change something?
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Old 17 November 2017, 22:15   #8
mark_k
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Don't know the answer but I'll upload an updated disassembly later.

There seems to be a mistake in the OMTI manual, on p.5-2 the definitions for the C/D bit are the wrong way around. (So 0 means byte being transferred is data.) But I guess you already know that since surely other OMTI-based drivers require that.

Edit: Updated disassembly
Code:
https://www.media!fire.com/file/ye710kysr4b6okd/billsdisk_disasm_20171117.tar.gz

Last edited by mark_k; 17 November 2017 at 22:42.
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Old 17 November 2017, 22:54   #9
Toni Wilen
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Hang is gone if STATUS IREQ is cleared when STATUS is read and phase is not status. So I guess hardware latches STATUS and software needs to read it once after status byte has been read.
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Old 20 December 2017, 22:36   #10
mark_k
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Maybe not much use for emulation, but FYI... Linux (used to) support XT-like controllers including the DTC-5150X, see drivers/block/xd.c.

Possibly more helpful to compare with your implementation, the PCem emulator supports that type of controller, see src/mfm_xebec.c.
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