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Old 01 August 2014, 01:11   #21
K.C.Lee
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Originally Posted by majsta View Post
Good luck.
Only one thing I didn't understand.
Why do you need external PLL?
It makes a bit easier to recompile other FPGA cores that uses a different clock input without having to play with the PLL setting in the source code. Also at some point if I want to play with pushing clock speeds like overclocking, I can dial in the new clock without recompiling the FPGA core.
Note that is only for part of a design e.g. memory controller as the video might get out of sync.

Amiga PAL (28.375MHz) or NTSC (28.636MHz) mode can now be run at their clock frequency and not just an approximation 28MHz(?). This PLL can generate frequency with resolution a few digits behind the decimal point and not just 1MHz increments like you would find in a PC.

The true story: Originally I was going to use it to generate the 48MHz and FPGA clock from a 25MHz for Ethernet. You pay about the same, but get the flexibility.
Then the layout got crowded. From a signal quality point of view and easy of routing, I have decided to stick individual clocks near the chips. I like the PLL,so it stays. It is a shiny $2 toy I want to play with.

Last edited by K.C.Lee; 01 August 2014 at 01:24.
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Old 01 August 2014, 11:21   #22
majsta
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Using external PLL does not make any sense.
You have enough internal PLLs inside FPGA and all of them can be used the way you described.
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Old 01 August 2014, 19:08   #23
K.C.Lee
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This board is built for myself at this point, so not everything needs to make sense to you.
If you want to question, go bug fpga arcade as they are probably using external PLL for their clocks too. See their chip labeled as Clock Generator.

http://www.fpgaarcade.com/punbb/view...p?pid=775#p775
>the three on board PLL are used:
>- one for SYSCLK (y0)
>- one for the PLL/NTSC Coder clock (colour burst frequency on y1)
>- one for VIDCLK (y4)

Note: onboard not onchip.


This PCB is not limited for computer emulator. It is also for my FPGA and ARM eval board. If I want to test out a PLL, where else would I do it?
I don't ask you why you spend that $2 on things, do I?

Oscillator: $1.77 vs Crystal: $0.60 + PLL $1.55
Cost delta = $1.77 - ($0.60+$1.55) = -$0.38 cost saving

for that $0.38, I give you 3 flexible programmable clocks. I think it is a good deal to get a bullet point on marketing.

It is my money and my board. Pay me enough, I would make a board without one just for you. I'll charge a standard consulting rate and in your case no discounts.
You can always design and layout your own board just like I did without any help. I'll make the schematic part open source at some point.

If I need a special odd ball frequency, I can make it. FPGA PLL is very limited vs this.

> Generates up to 8 non-integer-related frequencies from 8 kHz to 160 MHz
(3 in that package)
> Exact frequency synthesis at each output (0 ppm error)
> Glitchless frequency changes
> The device consists of two PLLs—PLLA and PLLB. Each PLL consists of a Feedback Multisynth used to generate
an intermediate VCO frequency in the range of 600 to 900 MHz. Either of these two VCO frequencies can be
divided down by the individual output Multisynth dividers to generate a Multisynth frequency between 500 kHz and
160 MHz.

I can ask for 123.456MHz and 2 other odd ball frequencies this chip will give it to me just like that. No approximation nor rounding off. Please show me that the FPGA PLL can do that. Oh yes and on the fly, not precompiled please.

Last edited by K.C.Lee; 01 August 2014 at 19:58.
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Old 01 August 2014, 20:20   #24
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Quote:
Originally Posted by K.C.Lee View Post
If you want to question, go bug fpga arcade as they are probably using external PLL for their clocks too. See their chip labeled as Clock Generator.
Interesting project you have here K.C.Lee. I don't think Majsta needs an FPGA Arcade He's done his fair share of FPGA development for the Amiga... http://majsta.com

Cheers and good work man!
Ed
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Old 01 August 2014, 21:03   #25
K.C.Lee
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I am a board level hardware guy first, not FPGA designer, so who I am to argue.

People already complain about not having enough features: memory, high res video DAC etc. when it is my own proto board and my time that I am paying for.

I put a decoupling cap per power pin on the chips and don't break return paths under my routes and some people would probably want to argue about that too.
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Old 02 August 2014, 01:39   #26
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I am working on a FPGA board (prototype)

Hi KC, awesome project!

When ppl ask for more ram etc I'm guessing it's because they like your project and would consider buying it when it's ready (assuming you would make more) so I'd say it's more compliment than criticism.

Personally I luv my a500's and so 32mb would be enuf for me.

Don't mind majsta's style, English isn't his native language and I don't think he intends to be so blunt but he has a proven track record building the Vampire A600 FPGA accelerator and has a wealth of experience.

Last edited by dJOS; 02 August 2014 at 01:49.
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Old 02 August 2014, 15:19   #27
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I hate to sound like an angry jerk, but I already explained the historical reason why it was there. I explained my own reasoning why I think I need it. I am not a FPGA guy, so may be he is right about being able to do everything he claims, but I don't want to risk removing parts and have to make an ugly mess of wire soldering it on later. I do know the PLL part a bit and play with their software so I know exactly what it can do. I want to try out a part in a prototype.

I planned it as it was a cheaper solution to make 3 clocks, (cost saving on 2) but it turns out the layout doesn't work that way. When everything is done, the cost difference isn't much. By then my parts are already ordered for checking my layout.

I had to make a decision, do I waste $8 shipping to buy a $1.77 cost part and rip out a section of the layout just to "save" $0.38? Do I remove a part that a competitor put on his board and risk not being to take advantage of the FPGA code with minimal changes if he actually releases it on a cold day in hell? They are also limited resources. So if the other design release a core that uses 5 PLL (they have 4 internal +3 external). May be they want to be jerks just to piss you off or really they found out they do need that. May be I *do* need to preserve that on chip PLL for my high speed BLVDS high speed serial expansion port for an accelerator that the other guys don't have.

Can you magically be able to make do with just 4 internal PLL without recoding it? Or that people could/would complain about not having that as a marketing feature? Talk is cheap when you don't have take the full responsibility for making that decision.

Not enough memory, lack of colour resolution those I can understand. They might not be my target market, but I do have ideas how I can cover them.

Sure people can be jerks and say it suck because it doesn't compete with a 20 years old high ended product aiming at a rich crowd, but at least that's telling me there are some marketing potentials. I looked at what is being offered in the current baseline products and the amount of memory they are offering. Do they say those products suck too?

Do I think 128MB is going to make a difference? Is 256MB the magic number? What is the cost to implement that to make the 10% people happy? By having the minimal # of chips to keep the signals clean so that I can run the chip as fast as possible. I am using 32-bit wide memory bus so that I can compete with DDR design without paying an extra $50 for my proto PCB. More memory bandwidth means that at some point I can get higher resolutions out of the FPGA. They probably never thought of that. May be they don't care. Feature creeps is one of the major killer of projects. I have real deadline and budget to keep.

Believe it or not, designing this board is my political statement to the existing product. I don't go on their forum and complain that their product suck. I don't care about retro gaming. I want networking, internet, HDD, USB, RTC and future expansion in the baseline product.

Sure you can speculate and talk all day. Has anyone actually done something about it? I fire my warning shot by showing that a guy can design a competing product at $200 in his home lab. By the way it is small and sexy too. Whether or not I actually follow up and make this a commercial product is a different matter. Until then, they would have something to think about at night.
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Old 02 August 2014, 18:34   #28
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I m sorry but I just wanted to help by asking specific questions and maybe providing another answer. I looked to your board and I was prepared to discuss few things. At the end I didn't liked the way you answered me thinking that I attacked you or your work somehow, truing to be arrogant and judging what you have done so far. That was not my intention.

Good luck, I m out

Last edited by majsta; 02 August 2014 at 18:45.
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Old 03 August 2014, 19:14   #29
K.C.Lee
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Just don't like the style of questioning for a decision that has been already made as if the question itself would have any effect for something that happened in the past. Board has already been made and it on a plane. Parts ordered.

If it breaks the system, surely I would look into that.
Something that's not needed, eventually may be I would decide to remove it. I am the board prime, boss and investor, I have the final say in the matter.

Given the reasoning that I *had* based on the history why the part was there and how the board evolved was apparently wasn't good enough for you or that you don't care about what I said.

The "yes it can", but without examples of "how" to do it for a layman like myself isn't productive. No examples means I can't use it. Nor have you address my concerns.
Not every one is a FPGA expert like you. Keep saying the same thing when I have given you more detail is not helping me.

For me it is a non productive feedback.

Last edited by K.C.Lee; 03 August 2014 at 19:33.
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Old 03 August 2014, 19:31   #30
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I agree with Majsta. You don't seem lo like any feedback saying what people doesn't think it's right.

Good luck with your things.
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Old 04 August 2014, 13:13   #31
majsta
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@K.C.Lee it seems to me that you have no idea how to talk with ppl involved in Amiga scene. At some point you will ask for the help but because your attitude no one will help you. Then you will start to beg for the answers and finally you will left the forum and Amiga scene blaming everyone else. After 16 posts of this forum you should be more humble than everyone and easily build confidence in your work. Here we have lot of people who are proven themselves in various project and you need to learn how to talk to them. From every your sentence I feel frustration about something. And I m not FPGA or Amiga expert but at least I m humble and grateful for the help I received from members of this forum.
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Old 04 August 2014, 15:45   #32
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Guys there is no need to think that anyone trying to insult each other - http://www.altera.com/support/device...-overview.html based on this i can see reason why external PLL - seem Altera is not so flexible as it should be and there is quite large market PLL's designed to work with Altera (but not only).
I sometimes use circuit which can be replaced by something else because it is easier for me - searching for solution which is cheaper by 0.50$ or similar have perfect sense for me when large sale production is going - any 0.5$ saving will multiple immediately by ten and hundred thousands devices giving significant reduction of costs (i.e. provide higher income margin) but for hobby design sometimes it is better to have separate IC that cost 1 or 2$ and trust me - i work with product where Intel was not able design simple VCO/DCO (it is faulty by design) and external VCO is required - mistakes happen to all - even such companies as Intel. Sometimes it is better to use dedicated device than struggle with design (i assume flexible clock source can be done on Altera but perhaps it will require to many resources).

So relax, all Amiga hobbyist appreciate all efforts to provide new HW/SW, sometimes we ask - "hey, perhaps You can do this different?" (our impression better) but at some point we don't know all implications of project thus i would say all designers should see this more like good opportunity to share some thoughts than negative feedback - We All interested to make Amiga better and alive!
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Old 09 August 2014, 04:53   #33
K.C.Lee
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Update:
Got PCB in the mail yesterday. Been soldering as fast as humanly possible.

It just got a little bit more real.





Passed basic sanity check. So right now ARM, FPGA and my CPLD JTAG are working. Still got lots of work to do.

BTW:This thread was here to show progress. I haven't explicitly ask for help at this stage.

Nice of robinsonb5 to offer FPGA code examples and Veda on another board offer board level manufacturing feedback.

I got to work on my people skill for sure, but nobody is perfect.

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Old 09 August 2014, 08:34   #34
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Nice soldering, looks very neat!
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Old 09 August 2014, 15:10   #35
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Originally Posted by K.C.Lee View Post
Update:
Got PCB in the mail yesterday. Been soldering as fast as humanly possible.
It just got a little bit more real.
I got to work on my people skill for sure, but nobody is perfect.
Excellent work!
I really like your board, even the PLL you put on it.
(I have the on my boards too ;-), just gives you more flexibility)
And you soldering skills are definitely better than mine ;-)

So keep it up, it is an interesting project!

Cheers
 
Old 09 August 2014, 16:22   #36
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Soapbox Racer? Excellent name!

Good to see the real thing taking shape - have fun!
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Old 23 August 2014, 00:52   #37
FrenchShark
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Hello,
just my 2 cents about Cyclone III PLLs.
You can do 28.636363 MHz and 28.375 MHz if you use 5 MHz clock input.
5 x 227 / 40 = 28.375
5 x 252 / 44 = 28.636363
With PLL dynamic reconfiguration, you can switch between the two frequencies on the fly.
If you really look for cost saving, getting rid of the audio DAC is good. 3rd order delta-sigma in HDL gives good results. And you do not have to do sample rate conversion to 48, 96 or 192 KHz.
Another good cost saving is using active serial configuration on the cyclone III and the remote update feature. This way, you do not need the ARM chip.
With a 16 MB SPI Flash and FPGA bitstream compression, you can get 30+ different FPGA configuration.
BTW, did you use the 128Mb Flash with 64 KB sectors or 256KB sectors ?
IIRC, only the 256KB sectors one was compatible with Quartus II.
Best regards,
Frederic

PS : I can see that your soldering skills are pretty good : 0402 and QFN components. Well done !
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Old 04 January 2015, 20:13   #38
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Update:
Passed basic sanity check. So right now ARM, FPGA and my CPLD JTAG are working. Still got lots of work to do.

BTW:This thread was here to show progress. I haven't explicitly ask for help at this stage.
Hello K.C., any news on this board? Having fun?
 
Old 05 January 2015, 13:03   #39
RedskullDC
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Hi K.C.,

Just stumbled across this topic, pics of your board look great!.

Quote:
Originally Posted by K.C.Lee View Post
If I need a special odd ball frequency, I can make it. FPGA PLL is very limited vs this.

.... Please show me that the FPGA PLL can do that. Oh yes and on the fly, not precompiled please.
Cyclone V devices actually incorporate those features:
User-mode re-config of the PLL's, as well as Fractional PLL modes.

From the CV manual:

"If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency synthesisremoving the need for off-chip reference clock sources in your design."

Unfortunately, they only come in BGA packages which complicates assembly

At the end of the day, it's your project, so as long as you are having fun don't take any notice of me or anyone else

Regards,
Red
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Old 02 July 2017, 16:17   #40
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Anybody know what happened to this?

Announcement 3 years ago, some bashing at the poor guy and now quiet ...
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