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Old 29 July 2014, 00:36   #1
K.C.Lee
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I am working on a FPGA board (prototype)

Just want to share this bit of new with you.

I am currently designing a FPGA board for running Amiga Emulation. It is a FPGA evaluation board that I have specifically designed for computer (rather than the other way around). Yes, I am well aware of some of the FPGA evaluation boards and the FPGA Arcade. They look very good specs-wise too.

Mine is very loosely based on the spec of the Mist - namely the FPGA resources and SDRAM size, but that's where the similarity ends. I tried to pick parts with decent performance value ratio as I am doing this out of my own pocket and am on a budget.

FPGA: Altera EP3C24 - Same density as Mist, but larger package for I/O
SDRAM: 32M Bytes - 32-bit wide data bus
PLL: Si5351, programmable clock x 3, programmable from ARM
ARM: Freescale MK22DX256VLF5 256kB FLASH, 64kB RAM, USB OTG, RTC
Audio: AKM Audio CODEC + TI DirectPath Headphone Amplifier
Storage: 2mm Parallel ATAPI connector (for 2.5" HDD), MicroSD socket, 16 onboard SPI FLASH. There are lots of under $10 bi-directional PATA - SATA1 converters out there.
Ethernet: Microchip ENC624J600 10/100 Base T
PS/2: 1 connector (connected to ARM), but can use with a splitter to connect to keyboard and mouse.
USB OTG: One port, 1.5Mbps/12Mbps (connected to ARM)
RTC: Real Time Clock (on ARM). ARM is powered under standby and have software power On/Off control of the rest of the board. There is Supercap backup in case the main power is out.
Video: VGA, RGB 6-bit R2R DAC, buffered
Expansion port: High speed serial link for a daughter card. It is for a processor or FPGA card etc. So if there is a more shiny FPGA, move the CPU core over there and run this card as a slave for its I/O.
Size: 10cm x 10cm. Width of a 2.5" HDD.

Current status: I have been designing the hardware for last 3 month with my own time and money. My blank proto PCB is on its way (25 days) from China. So realistically going to have put in another 2-3 months before I'll get it to work. Most of the extra features requires a lot of FPGA/firmware/drivers to work.

Project detail, pictures and logs hosted: http://hackaday.io/project/1347-FPGA-Computer
There are a bit more details over there. I'll get the schematic released under open source at some point. This is towards a contest, so that's extra motivation for me to finish this work. Not expected to win the top 5 prizes due to competitions. Hopefully, I'll at least get some recognitions.

You can read up there without registration. Or if you want, you can register and comment, complement etc. No one seem to say anything over there at the moment on my project. Wrong crowd I guess.
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Old 29 July 2014, 00:55   #2
Lord Aga
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Looks cool
And special congrats for this being a home, solo project. I'm a sucker for those things.
Please keep posting here. Inform us about this project.
Full support and all the best !
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Old 29 July 2014, 01:20   #3
K.C.Lee
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Thanks for the encouragement. I guess it beats blogging to myself without any feedback. Sometime I feel like I am in the middle of some very polite Japanese audiences that smile back, but not ask any questions.

What I do hope to get out of this is to "level-up" my skills. I tend to learn a lot more if I am stepping outside my comfort zone.
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Old 29 July 2014, 01:35   #4
Retrofan
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I like to know of these projects the same way I liked Gunnar's thread that was closed http://eab.abime.net/showthread.php?...&highlight=ban. He was banned and we don't know anything else since then.

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Old 29 July 2014, 01:53   #5
K.C.Lee
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I hope that's not the reason for being banned. I am more a hardware/board level person, so I can't comment on FPGA side of things.
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Old 29 July 2014, 02:07   #6
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Very nice!

One question: can the SD card be accessed directly from the FPGA, or does the µC "own" it?

Good call on the 32-bit wide SDRAM - it's much easier to mod an existing SDRAM controller's width than adapt it to DDR, and you always have the option of ignoring half the data lines and using an existing controller unmodified.

I'm looking forward to following this project's progress
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Old 29 July 2014, 02:42   #7
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I am going to do ignoring the other 16-bit memory bus until I get the rest of the board going. Even getting a network driver going would have a much higher priority than that. It is a chicken & egg problem to get a 32-bit datapath in the FPGA core developed. So I decided to do that first step.

I can't use DDR memory on a double sided and very crammed PCB anyways. DDR pretty much need a 4 layers board, controlled impedance and more board space for matching the PCB traces. On the other hand, Altera (and Xilinx) have DDR/DDR2 core available.

That's a 166MHz SDRAM part, but I don't know if the FPGA/PCB can go that fast. I did make the cleanest layout I can as well as stuffing 1 decouple cap per power pin to make sure thing are as good as they can be given the double side PCB limitation. I think there are around 100 decoupling caps on that board alone.

Originally I did plan to give the FPGA full access to the SD card (as in 4-bit acess and not slow SPI), but I had to change the connection to my CPLD which is responsible for the Ethernet/ATA. The outcome of that is that I had to widen that bus to 16-bit, which used up all those FPGA I/O pins. So now only the ARM has access to the SD and the 16M bytes SPI FLASH (last minute, but hey it is only around $2). The FPGA is a slave on the SPI bus.

On the other hand, the FPGA has a direct 16-bit data path to ATA via the CPLD. I am going to map the ATA interface to the same address as the one in the A1200 and let the 68000 get full access to it. That should be speedy for a change. At some point might write a driver and update the FPGA/CPLD and Amiga driver to allow for UDMA-33 which is as high as it would go. (Different ATA command set and also requires a hardware CRC for UDMA.)

Last edited by K.C.Lee; 29 July 2014 at 02:57.
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Old 29 July 2014, 03:22   #8
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Are the board specs set, any chance of increasing the memory?

I assume this FPGA is big enough to support AGA/RTG?
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Old 29 July 2014, 03:23   #9
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The project looks nice and I hope it would be finished. I noticed that there is a lot of love for Amiga hardware now days, like FPGA accelerators, RAM expansions, sound cards, and FPGA Amigas.

How are things in the software department is the Amiga core done? What are you using for testing your ideas?
Will you port MiST core to your board?
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Old 29 July 2014, 04:34   #10
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That SDARM is the largest one for that package. SDRAM is going EOL, so don't expect to be any larger one. Not going to use BGA packaging just for 64MB. 16MB for now until I can turn on the x32 databus to get the full 32MB. Given that I had been using 4MB/2MB Amiga in the past, so that's not a big issue for me.

I have only gotten the PCB layout finalized last week and got the board made. Got my confirmation email today that my PCB are going to be arriving in 25 days (give or take). Taking a mental break, that's why I joined this board today.

Then I have to figure how to solder them. Working with 0.5mm pitch, DFN and 0402 parts are not easy. I don't want to spend money on stencils ($20 which is a very good price) nor solder paste ($16), so I am going to try something else to reflow the board.

Haven't done anything with firmware/FPGA cores as this is a one man show. The next step on my list is CPLD and then ARM. I need to get a debug monitor on the ARM and port minimal firmware over to configure the FPGA. I am using a Freescale ARM chip and not the SAM7 chip (for package size, USB OTGa and cost reasons). This is my first time with ARM chip, but I can program 8-bitter and write my bare metal code from datasheet.

My very long term plan is to diverge from the ARM code base. I believe a RTOS is the way to go for my sanity and for things like USB support.

My verilog and VHDL is very rusty at the moment. MiST is the closest parent to the FPGA this new design, so I would start with whatever FPGA cores from that project. I read that he was using Pacman game for debugging MiST, so that would be a big test for memory, VGA etc. I have ordered a Chinese USB Blaster clone, so probably going to use their free logic analyzer (Spinal Tap) for debugging.

Yes, I am doing things as if things are not hard enough. But then again, I have always gotten the high risk and late start projects that one one else want to do.

I am looking forward to reach that stage of the project when 32MB is not enough or having worry about RTG. I have same amount of FPGA and memory resource as MiST, so my problems will also be MiST's problem.

I have an expansion connector with high speed serial link, so my logical move is to vacate the 68000 core from the FPGA on this board and pop in a daughter card with a shiny FPGA or FPGA with a processor. That should leave enough space for a larger graphic core. My original plan was to use the next sized up $70 FPGA that is in this footprint. It turns out that one has less I/O, so not usable for my design as is.

Last edited by K.C.Lee; 29 July 2014 at 13:44.
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Old 29 July 2014, 05:21   #11
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Attached are paper cutouts for my board. I was using them to check for component foot prints and making sure the connectors have right spacing. (missing Ethernet connector in picture as it is still in transit) It'll give you a sense of actual size of my board.

Also my youtube 2 minutes 3D walk around video to satisfy contest requirement. Figured that I have already gotten the 3D modeling for the board, so I threw in some text and canned music from youtube library. That was my first youtube video, first Sketchup 3D animation etc.

[ Show youtube player ]
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Old 29 July 2014, 10:45   #12
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2 comments: I'd really go for a 24-bit DAC to enable full AGA, and 32M ram sounds like something you'll end up wishing was umpteen times larger.
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Old 29 July 2014, 10:48   #13
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Quote:
Originally Posted by K.C.Lee View Post
I am going to do ignoring the other 16-bit memory bus until I get the rest of the board going. Even getting a network driver going would have a much higher priority than that. It is a chicken & egg problem to get a 32-bit datapath in the FPGA core developed. So I decided to do that first step.
Actually the 32-bit width should be a fairly easy mod. You might find the projects here: https://github.com/robinsonb5/ZPUDemos useful for debugging - the SDRAM tester in particular.
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Old 29 July 2014, 13:02   #14
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I wish you the best of luck with your project, but I have to say that 32MB of RAM is nothing short of pathetic in a modern device, a Blizzard 1260 supports 128MB and it was released 20 years ago.
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Old 29 July 2014, 13:18   #15
K.C.Lee
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Once again, this is for a contest. So there is a real dead line. As I am not building a 3D printer/laser/wireless/computer vision stuff/blinky lights/props, my chances to win the $200k prize is NIL. That's what the crowd over at Hackaday like to see unfortunately.

Based on judges' background, a few would appreciate what I am doing. If I get it working on time, I am likely to win $1k - $5k worth of useless prizes. They are the only ones that I am catering/marketing toward at this time. I'll take whatever over nothing. This card is also my resume.

I have closed off the PCB layout. Being shipped. Done. Part purchased. Done. Feature list closed. FPGA I/O completely filled, so no 32-bit DAC. PERIOD. Feature creeps is what kills projects. Having a product that make 75% people happy is better than a project that never make it out the front gate. See plenty of examples for that.

Look at my layout (over at my project log site and I won't repost here) and tell me where to put and route the parts. Everything was hand routed. This is rev. 15 of the layout because this is the only way to fit things into this while looking after the high speed signals and not breaking things. ~70% of board space is filled with parts and the rest are pretty much just routing. See last couple of my project log files and see how bad it is to squeeze 5mm space for a connector screw up.

32-bit real video DAC cost about $12. My budget was supposed to be below a FPGA eval board, but now it is already close to one. Why would I spend more of my own money/time on a prototype that I have to debug than a working FPGA eval board or a real product that have more features/faster/more memory? Ditto for the consumers.

Seen the latest "Halt and Catch Fire" episode? After seeing that someone selling a new product with my specs and then a Mac demo in the hotel room, what would you do? Think about that one.

I need to concentrate to do one thing at a time and you are not the target market right now. Myself and judges are. Contest prizes here. I'll revisit 'features" after the contest if there are sufficient commercial value to develop this into an actual product.

As far as I am concerned, a daughter card is the proper way to make a product for 2 different segments of the market. Incremental changes/upgrade over time that doesn't kill you initial investment. Also one man operation, so one thing at a time. Okay?

Find a FPGA card with bigger DDR/DDR2 memory on ebay. Make a small PCB for the BLVDS link connect to mate to my board. Use cat6 cable to link the two boards. Done. No need to wait for me.

I can copy & paste open source accelerator card design and change the bus to my high speed serial link. Voilą extra memory, faster processor on a daughtercard. I am also no longer limited to low density slow and much more expensive out of date SDRAM nor x16/x32 bus or to a 680x0 only processor. Don't know about you, but I want to put memory in the "Northbridge" not the slower "Southbridge" anyways.

Once I pushed off the I/O, connectors and misc stuff like ARM on this card, it is actually easy to do a board layout for with only FPGA (with optional CPU or SoC) and SODIMM. It is also like child birth, the 2nd one is easier.

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Old 29 July 2014, 13:40   #16
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Quote:
Originally Posted by robinsonb5 View Post
Actually the 32-bit width should be a fairly easy mod. You might find the projects here: https://github.com/robinsonb5/ZPUDemos useful for debugging - the SDRAM tester in particular.
Ah... You are the guy from Retro Rambling. I am a big fan of your articles. I changed from a x16 to x32 SDRAM after reading your blog about needing more graphic memory bandwidth for high res graphics. That decision took about 2 minutes even though I had to restart the design/layout.

I could also write a memory test (walking zero/one etc) on the ARM and read/write SDRAM on a minimum FPGA core via SPI in a pinch.

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Old 29 July 2014, 15:13   #17
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Ah... You are the guy from Retro Rambling. I am a big fan of your articles. I changed from a x16 to x32 SDRAM after reading your blog about needing more graphic memory bandwidth for high res graphics. That decision took about 2 minutes even though I had to restart the design/layout.
Glad you've found the blog interesting - as you've probably seen more recently I've managed to get resolutions up to 800x600@72Hz in 16 bit working from 16-bit wide SDRAM without completely choking off the CPU - so achieving the same resolution with 32-bit colour on your board should be pretty much effortless.

Quote:
I could also write a memory test (walking zero/one etc) on the ARM and read/write SDRAM on a minimum FPGA core via SPI in a pinch.
Yup indeed. Good luck with the project, anyway - should be a lot of fun!
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Old 31 July 2014, 07:21   #18
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One question: can the SD card be accessed directly from the FPGA, or does the µC "own" it?
I just thought of something. There is a 16-bit data path (multiplexed Address/Data with an address latch signal) from FPGA to the Ethernet & CPLD. The CPLD (XC9572XL) is there to decode address space for both. I place the ATA registers within the Ethernet unused register space and the CPLD translates the bus cycle into the ATA signals. The FPGA is the one that's driving the timing.

So if you are willing to "gut" the ATA, you can deselect the Ethernet chip by latching the ATA address space. At that point, you can simply bit-bang the ATA signals from the FPGA state machine with the data bus (via the CPLD with new bit file). When you are done, let the normal Ethernet bus cycle through. The Ethernet chip has 24kB internal Rx/Tx buffers, so can tolerate a bit of burst SD traffic.

OpenCore has "Wishbone SD Card Controller". Need a software driver for that. 4-bit SD mode should be a decent alternative to ATA for low power applications.

You can hang a SD/MicroSD socket with the full 4-bit SD mode access there with the rest of the I/O for something else. ATA pins are 5V tolerant, but driving 3.3V out with proper series terminations per ATA specs.

If using the ATA pins for SD, the SPI from ARM (already hooked up to the CPLD) can be muxed to "share" the SD while booting. Per SD specs, SD card needs to be power cycled to switch between SPI and SD mode.

There are all kinds of crazy thing you can do within the hardware limitations (under project detail on my URL) as this is a development card and things are programmable/hackable.

Found out today that ARM SPI to CPLD is a no go (before booting FPGA) as it burns too much resources. After the FPGA is loaded, the ARM could talk to both devices via the FPGA.
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Old 31 July 2014, 12:57   #19
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Good luck with your project, always good to see new Amiga related stuff being developed.
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Old 31 July 2014, 23:19   #20
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Good luck.
Only one thing I didn't understand.
Why do you need external PLL?
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