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Old 31 December 2012, 17:37   #21
mark_k
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Also it says the HSYNC reset pulse is 32usec long (which is about half a scanline period), though it looks shorter than that in the timing diagram. It looks to end about 1/3 of the way through the scanline in the diagram. CIA-B TOD counts on the rising edge of that so it will count at 1/3 to 1/2 the way along every other scanline.
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Old 12 February 2014, 18:42   #22
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Posting to this thread because I noticed a genlock-related Amiga Mail article and scanned it. Not sure whether this is relevant for WinUAE or not, but in case anyone is interested...
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File Type: pdf Amiga_Mail_Genlock_Article.pdf (383.4 KB, 123 views)
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Old 13 February 2014, 14:32   #23
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Hmm... from the third page in that PDF file:
Quote:
For PAL Amiga models, the genlock device must provide the Amiga with horizontal and vertical reset pulses with the following rates:

HSY* line: Active-low pulse of proper duration every line (i.e. 63.99 uS or 15.625 KHz).

VSY* line: Active-low pulse of proper duration every two fields (i.e. 39.99 mS or 25.0 Hz).
If that's correct, for PAL Amiga/genlock CIAB TOD will count every line, as opposed to every other line for NTSC. But there doesn't seem to be any code in graphics.library to account for that. Meaning, if you try the test disk I uploaded before (drag the icon on Workbench), movement could be smooth with an NTSC Amiga/genlock but flickery with a PAL Amiga/genlock. It would be easy to patch Kickstart to fix that bug/deficiency, but I'm guessing no-one cares enough to do it.

It would be great if someone with access to a PAL Amiga + genlock could check that.

Last edited by mark_k; 13 February 2014 at 14:40.
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Old 13 February 2014, 15:39   #24
Toni Wilen
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Yeah, if the document is correct, only NTSC genlock has half-rate hsync pulses.

EDIT: it also says vertical is "half-rate" only in interlace, non-lace is normal, both PAL and NTSC.

Last edited by Toni Wilen; 13 February 2014 at 15:52.
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Old 13 February 2014, 20:13   #25
mark_k
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Quote:
Originally Posted by Toni Wilen View Post
EDIT: it also says vertical is "half-rate" only in interlace, non-lace is normal, both PAL and NTSC.
I don't think it does say that necessarily. My reading of it is that the vertical reset pulses provided by the genlock are always at half-rate (page XII-29). Or perhaps the text on that page was written assuming that the external video source is spec-compliant NTSC/PAL (so always interlaced)?

The vertical counter explanation on page XII-28 (in interlace mode vs in non-interlace mode) is I think referring to the Amiga display mode rather than the external video source connected to the genlock. But it isn't completely clear to me:
"In non-interlace mode the vertical counter is set to operate with either long or short fields, depending on the last value that the software wrote to the FRAME bit. In this mode, whenever an external VSY* pulse is applied, the counter is reset to line count 000 (first line) at the beginning of the next horizontal line."

I assume the FRAME bit means the LOF bit in VPOSR/W. Could that be taken to mean, with half-rate vertical pulses, for a field with no VSY* pulse the vertical counter rolls over to 0 after counting to the appropriate value depending on the LOF bit. And when there is a VSY* pulse the vertical counter resets to zero???

This needs testing on real hardware.
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Old 13 February 2014, 20:30   #26
Toni Wilen
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I missed the second page which says "every two fields". I guess technically "normal" rate should work in non-lace modes. (even if it is against the spec)

But Agnus vertical counter is 9 bits (OCS) or 11 bits (ECS). It does not wrap around at the end of field. Perhaps this is what "setting long-field condition" means? There is internal register that stores line where next line should end, even if there is no vsync pulse.
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