Custom Flashrom design for Amigas

[kipper2k]

The socket will be able to have a rom piggybacked so no problem there, i am assuming that when a rom is piggybacked then CE must be disabled on the Flash in order to allow the piggybacked rom to takeover

[dJOS]

Any one want to write me a custom a500 1.3 rom with gayle IDE support based on my legally owned 1.3 rom?

Cause I'll defiantly take one kipper if someone can assist me.

[RedskullDC]

Hi Toni, et al.

Originally Posted by Toni Wilen

Of course some extra logic is needed because Gary/Gayle blocks any write attempts to ROM regions.

Here is my wanted feature list: http://eab.abime.net/showpost.php?p=689709&postcount=33

Could I pick your brains on a couple of points?
[Could work it out myself, but I figure you have explored it thouroughly already ]

So *ROMEN is not asserted during a write cycle to the following regions?:
A80000 to B7FFFF 1 MB System ROM selected
E00000 to E7FFFF 512 KB System ROM(lst half if 1MB ROM)
F80000 to FFFFFF 512 KB System ROM(2nd half if 1MB ROM)

I assume that *OE is not asserted either during a write cycle to those locations?

---
I'm working out a circuit to use the MX29F1615 1Mx16 Flash chips at the moment. There already seems to be support built into the GAYLE chip (and on the A1200 motherboard) to support variable flash programming voltages via the PE5 and PE12 outputs.

Have you experimented with these output pins?

The Linux GAYLE includes:
http://os1a.cs.columbia.edu/lxr/sour...asm/amigayle.h
show the bit masks to control these pins:
(and also ROM access times?)

/* GAYLE_CONFIG bit def
(bit 0-1 for program voltage, bit 2-3 for access speed */

#define GAYLE_CFG_0V 0x00
#define GAYLE_CFG_5V 0x01
#define GAYLE_CFG_12V 0x02

#define GAYLE_CFG_100NS 0x08
#define GAYLE_CFG_150NS 0x04
#define GAYLE_CFG_250NS 0x00
#define GAYLE_CFG_720NS 0x0c

The way I read it, the GAYLE CONFIG register is at $DB0000?

-----

Most of your wish list looks do-able by the way.

The MX29F1615 is a drop in replacement for the stock kickstart roms.
2 in a 1200 will give 2MB kickstart functionality with a slight change to either the motherboard, or a fly lead to A22 if using a kickstart adapter board (no motherboards mods necessary in that case).

Cheers,
Red

[Toni Wilen]

Originally Posted by RedskullDC

So *ROMEN is not asserted during a write cycle to the following regions?:

I meant only Gary, I haven't tested Gayle. (All my logic analyzer tests done using A500, much easier than SMD stuff)

Gary and Gayle are very different.

Gary: ROMEN goes to ROM output enable pin. Chip select hardwired to active state. ROMEN = Only active if read access.

Gayle: ROMEN goes to chip select pin. RW goes to Output enable pin. It looks like Gayle has built-in write support for ROM regions (schematics also shows alternative flash rom option)

I have no idea how _FLASH_CEU and _FLASH_CEL pins work.

(For some reason I didn't notice that Gayle seems to have nearly full flash support built-in, at least if _FLASH_CEx work.. I guess I have used A500 too much..)

So for Gayle based Amigas "only" adapter + ROM socket on top is "needed". (with jumper/switch to enable/disable socketed ROM)

/* GAYLE_CONFIG bit def

These are PCMCIA registers but looks like programming voltage selection pins are shared with flash stuff. But do we really have to use chips with VPP requirement and only 100 write cycles vs modern +5v only with 100000+ cycles + internal programming algorithms (no need for special timings)?

I am quite sure timing selection bits are PCMCIA only.

The way I read it, the GAYLE CONFIG register is at $DB0000?

$DAB000

[hooverphonique]

Originally Posted by kipper2k

The socket will be able to have a rom piggybacked so no problem there, i am assuming that when a rom is piggybacked then CE must be disabled on the Flash in order to allow the piggybacked rom to takeover

Yes.. CE (and possibly OE) must only be asserted for one rom chip at a time.

Presuming you are using a wire-wrap socket that has its pins going through the pcb and into the original rom socket (which it looks like you're doing in the layout you posted), how will you accomplish this?

[kipper2k]

Originally Posted by hooverphonique

Yes.. CE (and possibly OE) must only be asserted for one rom chip at a time.

Presuming you are using a wire-wrap socket that has its pins going through the pcb and into the original rom socket (which it looks like you're doing in the layout you posted), how will you accomplish this?

Hi,

to accomplish the active chip...

Remove the trace from the Flash rom CE pin on the 42 pin connector (pin 11 on the 42 pin socket) and route the Flash CE output to a toggle switch or jumper (High/Low).

With only the flash rom installed, flip jumper/switch to ground. When KS Rom inserted, flip the switch (or Jumper) to High. THis way the Amiga will not see the Flash rom and just read the piggy backed KS

[RedskullDC]

Hi Toni,

Originally Posted by Toni Wilen

I meant only Gary, I haven't tested Gayle. (All my logic analyzer tests done using A500, much easier than SMD stuff)

(For some reason I didn't notice that Gayle seems to have nearly full flash support built-in, at least if _FLASH_CEx work.. I guess I have used A500 too much..)

These are PCMCIA registers but looks like programming voltage selection pins are shared with flash stuff. But do we really have to use chips with VPP requirement and only 100 write cycles vs modern +5v only with 100000+ cycles + internal programming algorithms (no need for special timings)?

$DAB000

Thanks for the tips.
Looks like I will have to fire up the logic analyser on the weekend to confirm exactly what is going on with GAYLE in my 1200.

----

Only benefits for me using the MX29F1615 chips is that:
1. I have a few already to get started with.
2. They are DIP42, so plug right into the kickstart sockets, or easily piggy-back existing chips. Not everyone can solder tsop chips easily
3. Program algorithm is actually the same as a 29F160 (apart from raising the *byte/vpp pin to 10V). Software will be nearly identical.

Going forward, the chips with 100K+ write cycles are definitely preferrable.

The PE5 and PE12 pins could forseeably be used to control 512K/1MB/2MB rom layout if using 5V only chips....

Still kicking some ideas around in my head, will have a better idea after looking that the signals coming out of GAYLE.

Cheers,
Red

[kipper2k]

Originally Posted by RedskullDC

Hi Toni,



Thanks for the tips.
Looks like I will have to fire up the logic analyser on the weekend to confirm exactly what is going on with GAYLE in my 1200.

----

Only benefits for me using the MX29F1615 chips is that:
1. I have a few already to get started with.
2. They are DIP42, so plug right into the kickstart sockets, or easily piggy-back existing chips. Not everyone can solder tsop chips easily
3. Program algorithm is actually the same as a 29F160 (apart from raising the *byte/vpp pin to 10V). Software will be nearly identical.

Going forward, the chips with 100K+ write cycles are definitely preferrable.

The PE5 and PE12 pins could forseeably be used to control 512K/1MB/2MB rom layout if using 5V only chips....

Still kicking some ideas around in my head, will have a better idea after looking that the signals coming out of GAYLE.

Cheers,
Red

Thanks for looking at this Red

[hooverphonique]

Originally Posted by kipper2k

Hi,

to accomplish the active chip...

Remove the trace from the Flash rom CE pin on the 42 pin connector (pin 11 on the 42 pin socket) and route the Flash CE output to a toggle switch or jumper (High/Low).

With only the flash rom installed, flip jumper/switch to ground. When KS Rom inserted, flip the switch (or Jumper) to High. THis way the Amiga will not see the Flash rom and just read the piggy backed KS

Ahhh... What I didn't catch at first was, that you designed it so you cannot leave the KS rom chip in while using the flash

[RedskullDC]

Hi Kipper2k, Toni, et al.

Originally Posted by kipper2k

Thanks for looking at this Red

Little bit of an update...

Gave up on the notion of using the 29F1615 chips...
As Toni pointed out, the 100x program cycles is a little restrictive.
Besides, I found a couple of 29F800's in my junk box, with SO44->DIP44 adapters to match.

---

I've worked out a circuit for the 1200 which satisfies (most of) Toni's requirements:

- in-circuit programmable
- small enough to fit inside an A1200 (socket adapter + SMD flash chip + some control logic chip)
- rom switcher (2MB 5v flash chips are still commonly available)
- configurable switcher or large (1M/2M) rom support

This one is not so easy:
- manually switchable backup boot flash (that can't be accidentally erased or overwritten)
Will have sockets for the original kickstart chips, so there is no way to "lose control" of the machine anyway.

This can always be added later:
- solder pads for signals that are not available in rom socket
Not even at prototype stage yet.

-----

Circuit uses 2 x 29F800 flash chips, couple of switches and a 74LS157 multiplexer.

Features:
Original 512KB Kickstart Roms or
2 x 1MB Flash kickstart spaces or
1 x 2MB Flash kickstart space.
all switch selectable.

In the following memory areas:
A80000 to B7FFFF 1 MB System ROM (1st half if 2MB rom)
E00000 to E7FFFF 512 KB System ROM(lst half if 1MB ROM, third 512K if 2MB)
F80000 to FFFFFF 512 KB System ROM(2nd half if 1MB ROM, top 512k if 2MB)

In-circuit programmable, naturally.

Flash chips are programmable only when Kickstart is active, and automatically write protected when they are active.

Software looks relatively easy, the algorithms haven't changed much from when I wrote the original code for the Kickflash500 project. Just a case of expanding it to handle 32bits.

Will make up a prototype on the weekend, time permitting.
Stay tuned!
---

An option for 4 x 512KB Flash images is not hard to add, but does make the circuit a little more complicated.
Is this really important to anyone?

Cheers,
Red

p.s. Haven't forgotten those of you with 16bit Amiga's.
Once this is working/proven, will do something for GARY based Amiga's.

[mfilos]

4x512KB isn't that important imho.
I mean what's the point of having for example an 1.3 (doubled), 1.3+scsi, 2.05, 3.1?

My ultimate ROM would have been an 2MB one, having the ability to add:
- A custom 1MB ROM Kickstart 3.9 ROM plus...
- A doubled or quadrupled RON to fill the 1MB space.

For example:
4x 256KB for an 1.3 ROM
2x 512KB for an 1.3 + scsi ROM
2x 512KB for an 3.1 ROM

[hooverphonique]

Originally Posted by RedskullDC

Gave up on the notion of using the 29F1615 chips...
As Toni pointed out, the 100x program cycles is a little restrictive.
Besides, I found a couple of 29F800's in my junk box, with SO44->DIP44 adapters to match.

Well, the 29F1615 are in fact eeproms, so no wonder the number of cycles is small ;-)

are those adapters home made? I trawled the net for suitable SO-DIP adapters, but didn't find any..

Originally Posted by RedskullDC

p.s. Haven't forgotten those of you with 16bit Amiga's.
Once this is working/proven, will do something for GARY based Amiga's.

remember that big-box amigas also use gary, while using 32 bit rom access ;-)

[RedskullDC]

Hi hooverphonique, et al.

Originally Posted by hooverphonique

Well, the 29F1615 are in fact eeproms, so no wonder the number of cycles is small ;-)

are those adapters home made? I trawled the net for suitable SO-DIP adapters, but didn't find any..

True (regarding the 29F1615). The multivoltage requirement also requires more circuitry.

I got the SO44->DIP44 adapters from Ebay for less than $1 each:
http://www.ebay.com/itm/230401592014

Cheers,
Red

[Toni Wilen]

Originally Posted by RedskullDC

- manually switchable backup boot flash (that can't be accidentally erased or overwritten)
Will have sockets for the original kickstart chips, so there is no way to "lose control" of the machine anyway.

Yeah, original rom socket is good enough backup back flash solution.

An option for 4 x 512KB Flash images is not hard to add, but does make the circuit a little more complicated.
Is this really important to anyone?

2x1M is fine with me. (But 4 banks would be nice when testing old A500 stuff, not that important)

btw, F00000-F7FFFF is also fun region because KS ROM always scans it for residents and there is also "$1111" direct jump option. Just put some resident modules there and it automagically works, no need to rebuild whole kickstart.

[RedskullDC]

Hi Toni,

Originally Posted by Toni Wilen

btw, F00000-F7FFFF is also fun region because KS ROM always scans it for residents and there is also "$1111" direct jump option. Just put some resident modules there and it automagically works, no need to rebuild whole kickstart.

That presents a minor problem actually...

The *ROMEN signal is not activated during a write cycle to the ROM memory areas. (At least not on my 1D4 GAYLE-01 board).
The *FLASH signal is activated during a write within the 512K flash area.

I'm using the 512K Flash "window" to program the 29f800's in 4 blocks of 512K.

With the design as it is, part of the 29F800 will be visible in the flash space when the kickstart roms are active, hence they will be scanned for residents etc.
This may not always be desirable

Will have to add a way to disable the Flash chips entirely when the original Kickstart chips are active.

Just as well I hadn't started building anything....

Cheers,
Red

[kipper2k]

From what i was reading Red, holding CE# high will disable the flash chip, i redone my design a bit to allow the swapping of KS and flash rom...

[Toni Wilen]

Originally Posted by RedskullDC

With the design as it is, part of the 29F800 will be visible in the flash space when the kickstart roms are active, hence they will be scanned for residents etc.
This may not always be desirable

Residents won't cause problems because both ID (4afc) and following address must point to ID. Address check will fail if ROM is not in original address.

But early $1111 check will probably cause problems. (If word at $f00000 == $1111, jump to address $f00002)

Any possibility to have one of the 512k banks appear at f00000? Even jumper that allows between e80000 and f00000 would be nice. (nice to have, not required)

[RedskullDC]

Hi Keppr2k,

Originally Posted by kipper2k

From what i was reading Red, holding CE# high will disable the flash chip, i redone my design a bit to allow the swapping of KS and flash rom...

Yep, that's correct on the *CE high disabling the flash chip.

---

Was having a look at the Schematics for both V1 and V2 A1200 motherboards last night.

Depending on the A1200 board variant, the *CE signal on the Kickstart sockets is either:

V1 : *ROMEN from Gayle
V2 : GND.

The *OE (output enable) signal on the Kickstart sockets also vary:

V1 : *OE from Gayle
V2 : *ROMEN & *OE (and)

Having *CE connected to ground (permanently enabled) on the V2 boards gives a slightly faster access cycle on the ROMS, at the expense of using more power.

Since it's permanently enabled, this means that if you connect the *WE to a flash rom in a V2 motherboard, it will theoretically respond to write cycles anywhere in the memory map.
(Well, anywhere that responds with the usual DSACK cycle and not a bus error).
Chance of spurious writes are highly unlikely however, due to the required unlock sequence built into every write cycle.

Did a bit of work on the prototype tonight, got both the 29F800's soldered up to the adapters...

---

Kipper2k: Are you using Eagle for your board design?
Any chance of posting the files for your flash adapter board?
Are you interested in laying it all out when I get it finished?

Cheers,
Red

[RedskullDC]

Hi Toni, et al.

Originally Posted by Toni Wilen

Residents won't cause problems because both ID (4afc) and following address must point to ID. Address check will fail if ROM is not in original address.

But early $1111 check will probably cause problems. (If word at $f00000 == $1111, jump to address $f00002)

Any possibility to have one of the 512k banks appear at f00000? Even jumper that allows between e80000 and f00000 would be nice. (nice to have, not required)

Yep, I've modifed the circuit to be in one of 3 states:

1. KS enabled in $F8, FLASH disabled.
2. KS enabled in $F8, FLASH enabled in $F0 space (2 x 512K banks switchable).
3. FLASH in 2MB space, or 2x 1MB images in $E0/$F8 spaces switchable and KS disabled.

Nothing is set in stone at the moment, still thinking of other ideas...
Have to make the circuitry as simple as possible due to the space restrictions...

Do the exec startup routines just scan the 512K bank at $F0, or do they scan the second half of a 1MB rom at $E0 as well?
How about the $A8-$B0 areas?

Cheers,
Red

[Toni Wilen]

Originally Posted by RedskullDC

Do the exec startup routines just scan the 512K bank at $F0, or do they scan the second half of a 1MB rom at $E0 as well?
How about the $A8-$B0 areas?

F0 is always scanned.
AFAIK only some ROM versions scan E0 region. (Possibly CD32 ROM only?)