First Amiga 600 FPGA Accelerator - Vampire 600

[cpiac64]

Bravo!!!!!!!!!!!!!!!!

if you need components, insert a list

[FrenchShark]

Originally Posted by alexh

I don't believe that any FPGA (at what we would consider a reasonable price) is going to be able to run a fast 68060 at 80MHz together with a DDR core etc. I think what we'll get is a version of T68 (68000) + DDR core running at 80MHz. The price of the FPGA + boards will almost certainly be as high as existing turbo cards.

So don't all throw away your 060 turbo boards. Even the most expensive FPGA's of today will struggle to replicate a compatible 680x0 close to the real computational speed of a 68060 at 50MHz

But as Jens' has shown, improvements in the memory controller can have amazing speed boosts compared to the original Amiga Turbo cards.

Add to that FPGA's could be programmed (if they were big enough and fast enough) to make all 680x0 opcode instructions single cycle. This would be a huge boost over the original CPU's.

The problem comes in that the original chips (especially the 060) had many many complex speed boosts themselves. Their caching, branch prediction and super scaler architectures are all advanced techniques not yet fully reverse engineered.

Tobias' great work on T68 and Jakub's work on adding 020 instructions and stack frames etc. is in it's infancy compared to these features.

They will come, in time.

I totally agree with Alex, current low cost FPGAs will allow you to get 030 performance. Moreover, Altera Cyclone might not the FPGA with the best performance/price ratio. This might change with the new Cyclone V.

I also working on a 68k core, my current approach is to have it micro-programmed, max clock is ~90 Mhz. It is fully synchronous with the cache and the SDRAM controller.
Currently, it is not designed for speed but for size (~1500 LEs).

The 68k is one of the most complex CPU to replicate, with the 56 instructions, the 13 addressing modes and the 3 operand sizes, there are around 1400 cases to test.

Regards,

Frederic

[majsta]

Originally Posted by cpiac64

Bravo!!!!!!!!!!!!!!!!

if you need components, insert a list

Thank you but I allready have all of the components for more then 100
boards.

@FrenchShark
I m so happy to see your posts again, posts related to this topics. You know that you helped me a lot with this, and you had time to answer all of my stupid questions. I wanted to talk with you more and more but for some time I could not find you anywhere. I spend number of hours to trace your mail, name, address or anything to contact you because you and few other people are only in the world who can make something related to this topic. Goal is to have open hardware base and to make something to place this computer in the place where its belong. We need to work together, and work every day hard, like I m doing for past year, working on this project more then 10 hours per day, every day. Open hardware base with tutorials web site is going up in few days.

[FrenchShark]

Originally Posted by majsta

Thank you but I allready have all of the components for more then 100
boards.

@FrenchShark
I m so happy to see your posts again, posts related to this topics. You know that you helped me a lot with this, and you had time to answer all of my stupid questions. I wanted to talk with you more and more but for some time I could not find you anywhere. I spend number of hours to trace your mail, name, address or anything to contact you because you and few other people are only in the world who can make something related to this topic. Goal is to have open hardware base and to make something to place this computer in the place where its belong. We need to work together, and work every day hard, like I m doing for past year, working on this project more then 10 hours per day, every day. Open hardware base with tutorials web site is going up in few days.

Hello,

I was busy with VHDL/Verilog dev. and my new job. I did not check my messages for a while.
I like the idea of making FPGA based accelerator, the problem is that the original HW can break any time. Moreover, it is not so much more expensive to make a complete system.
I wish I could jump in on this project but I do not have time.
It looks like you are still missing the SDRAM controller. This is a big piece, especially DDR. You really need to understand the different timings relationships and constrain correctly your design.
My first SDRAM design had 1 read error every 1 billion access because of a silly mistake. That does not seem to be a lot but that's enough to mess it up.

Regards,

Frederic

[majsta]

I know that you don't have time to help with this project, but when you see hardware part I m shore that you ll contact me first to help me, because there is no way to see board like this every day. I told you that main problem for me now is to have 100% working hardware, and for software I don't care right now, because when boards goes to market anyone could make better and faster cores and with the tutorials on the web site I hope one day we will have large base of codes for download. One more idea is that this system is overclock ready, so do it whatewer you want with it. Also I have confirmations that my hardware design is ok from Philips(NXP), TI, Analog devices, and much more. There are more then 10 companies who wanted to give me all of the parts for free just to promise that I ll use their products. They send me a lot of devices that I ll use. Also few phone calls from the USA to give away all of my work, and to work for them. No way I said this is open project. Also one small article about this in Amiga Future 92. So I can tell you this you helped me so much that you can't imagine, and I just know that you ll come back to help me again Because this is big big project, but let's wait to see hardware in my hand. Also you are talking about standalone computer based on FPGA. Hmmmm I have to tell you that I allready done that one month ago. He is ready for production, but let's go with this project first.

[alexh]

Originally Posted by FrenchShark

The 68k is one of the most complex CPU to replicate, with the 56 instructions, the 13 addressing modes and the 3 operand sizes, there are around 1400 cases to test.

Sounds like you need System Verilog & UVM constrained random + PLI C-Model

[FrenchShark]

Originally Posted by alexh

Sounds like you need System Verilog & UVM constrained random + PLI C-Model

I use Icarus verilog along with the musashi 68k emulator and a disassembler compiled as a VPI module.
I have a test ROM that is executed by the softcore and by musashi.
After each instruction execution, registers are dumped by both models and compared.
Not as sophisticated as what you have described but it works and it is free

Regards,

Frederic

[cpiac64]

@majsta
i need a socket for cpu a600 for new expansion with ram 4mega, is a special components or is a catalog, have you a code or part number?

[majsta]

What socket do you mean socket for MC68000? PLCC-68 socket is the one you can use, there are many versions of this socket thru hole or surface mount. Thru hole is harder to use because of pin configurations you need to understand and with surface mount you can connect MC68000 to fast ram in 10 minutes.

[billt]

Originally Posted by FrenchShark

I use Icarus verilog along with the musashi 68k emulator and a disassembler compiled as a VPI module.
I have a test ROM that is executed by the softcore and by musashi.
After each instruction execution, registers are dumped by both models and compared.
Not as sophisticated as what you have described but it works and it is free

Do you have an example of how to set it up that way? Sounds cool.

[majsta]

Today received, lets goooo, everything is going ok

[majsta]

first tests, just to find out does programmer detects board cyclone and to light up led from the vampire eye

[ Show youtube player ]

[Stedy]

Hi,

An interesting project you have here

One issue you may not have considered, how long does the FPGA take to boot and how will you disable the 68000 until the FPGA is configured?

Some new FPGAs (Xilinx Spartan 6 for example) take upto 3 seconds to configure at power on. Some of the Altera FPGAs have similar boot times.

If you post the part number of the FPGA, I'll check the boot up time for you.

Bye,

Ian

[majsta]

MC68000 is disabled from the start using BR. Part number is EP2C8Q208C8, but for now there are lot of problems with VHDL. I asked some of the people to help out and we will see... I want to speed up things, I can solve those problems but I ll need more and more time and with their help this could be done in few minutes...

[majsta]

Need help with VHDL. I send more then 20 mails and PM and I just can't beleive that noobody wants to help after I finished hardware part. I m hardware kind of person, and can build alone hardware part but I m having lot of problems with VHDL, so please can we finish this project. I just need some guidance for solving some VHDL problems, my codes in VHDL does not work
TG68 has address bus 31 downto 0 and I need 23 downto 1 also for the start I don't need to have some fast version 14Mhz could be fine, also there are other signals, clock problems. We have working hardware design now, and it is checked number of times by me and from many more people. I know that I also can finish VHDL code but I ll need more and more time and with someones help this could be done in matter of minutes. Please spare some time to help me because I worked over one year to get working hardware part.

[NovaCoder]

Try talking to Mike www.fpgaarcade.com maybe he can help you?

[majsta]

Thank you I just send him email. Problem is that there are only few persons who can help, and they have their own projects. But it would be a shame to left this project unfinished.

[majsta]

First design was wrong, next one is on his way for production. There was some problems with CLK from the Amiga board and some other signals, and problem wasn't in VHDL like I was thinking. In next design we shall see how all works. But I don't think that this new design could be final and I should find more errors later, but in the first design I was able to use external clock from 50Mhz crystal oscillator to test that some parts of the design are OK. In the new design I ll try to make something different than before regarding to input and output signals and bidirectional ones. I ll try to make cyclone decide in what direction signals should go, to control with cyclone voltage level translation between Amiga board and Cyclone and vice versa. It is the only way, and I was not thinking like that when first design is created. Shore this could be handled with easy way but I want to have all controls in my hands...

[FrenchShark]

Originally Posted by majsta

Need help with VHDL. I send more then 20 mails and PM and I just can't beleive that noobody wants to help after I finished hardware part. I m hardware kind of person, and can build alone hardware part but I m having lot of problems with VHDL, so please can we finish this project. I just need some guidance for solving some VHDL problems, my codes in VHDL does not work
TG68 has address bus 31 downto 0 and I need 23 downto 1 also for the start I don't need to have some fast version 14Mhz could be fine, also there are other signals, clock problems. We have working hardware design now, and it is checked number of times by me and from many more people. I know that I also can finish VHDL code but I ll need more and more time and with someones help this could be done in matter of minutes. Please spare some time to help me because I worked over one year to get working hardware part.

Hello,

you can ignore A[0], it is just used internally by the TG68 to generate uds_n and lds_n :

This is from the TG68 source (lines #402-403 in my file) :

lds_n <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
uds_n <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';

datatype encoding is: 00 = byte, 01 = word, 1x = long.
state encoding is : 00 = instruction fetch, 01 = internal op. (no bus access), 10 = data read, 11 = data write.

you can also ignore A[31..24] if you just access 16MB. I think this is the case for the moment.
Once your RAM works on your board, you have to decide where you map it and do an address decoding for your RAM and one for the 16MB space that represents your Amiga mainboard.

PS : it would be better to use a Cyclone III or even IV (cheaper) : their PLLs accept frequencies down to 5 MHz so 7.09 MHz is not an issue.

Regards,

Frederic

[majsta]

Since I send you that message I solved those problems Now I m in the process of waiting of new dev boards. Also on PM you told me that I should not use white boards for prototype ones. I know that now I allready ordered green ones In the design there are many modifications, also added few more parts like clock buffer to create number of 7.09 clocks and drive them to I/O of cyclone and one to clock multiplier who multiply that clock X2 and then goes to PLL1 input. But main problems here are regarding PLCC-68 socket and those problems are solved, also in new design level shifters will be controled with cyclone and this is importand for the bidirectional signals like DATA. Input directions of the level shifters will change regarding to data_in or data_out. So main problem for now is that 7.09Mhz signal who goes directly to I/O of cyclone, can it be used with Cyclone II, because as we know cyclone II can't use anything below 10Mhz, but I have some ideas. New codes in VHDL are ready, only waiting for boards to arrive. That is the main reason why I didn't talk so much here. I don't want to talk untill I have working board, too much time is spend here without working board. But I lost so much time because for every design change I need to wait about 30 days to get that part and then to test it. If I could have PCB manufacturer in my country and some electrical store then every design change and testing should not take longer then few days, but in this case it is too long...