DMA debugger and 14Mhz 68K

[ovale]

Hello Toni,

I was playing with the visual DMA debugger (v -4, Winuae 2.8.0) and tried to change the 'cycle-exact CPU emulation speed' to 4x.

With my surprise the black & gray pattern are still visible in the DMA debugger.
I supposed that a 14Mhz 68K uses all the available access slots.

I expected, where not in competition with DMA, only gray dots visible.
Instead, regular columns of gray dots are visible.
See the attachment.

It seems the 68K doesn't have access to 2 consecutive slots or most of the instructions don't use continuously the RAM.

Can you explain the behavior?

Thanks for your hard work!

[Toni Wilen]

14MHz 68000 only increases speed of instructions that have multiple idle cycles (mainly shifts, multiplication and division), everything else is still as fast (or slow) as standard A500, including all memory accesses.

Agnus and Gary controls all bus timings. CPU is a slave in 68000 based Amigas.

[ovale]

In another thread you said that the CPU is free to use even or odd cycles.
I inferred that it could used both.

If I understand what you are saying, Gary/Agnus still force the CPU to use half the bandwidth even if there is no competition on the bus.

Why put such limitation? Or better, from where it originates?
Is it present on A2000 and A3000 too?

Just checked cycle exact A1200 and the behavior is the same (turrican 2).

I'm confused ...

[Toni Wilen]

Originally Posted by ovale

In another thread you said that the CPU is free to use even or odd cycles.
I inferred that it could used both.

CPU memory cycle can _start_ during odd or even dma slot but 68000 memory access cycle is still 4 cycles and it always takes (at least) 2 dma slots.

Normally bus would be completely allocated for the CPU during memory access cycle but Amiga uses trick that allows it to interleave CPU and DMA cycles.

When CPU does addressing part of memory cycle (~first half of memory cycle, simplified), Agnus "only" stores the CPU address but it can also simultaneously do DMA transfer to/from chipram because data bus is still free (there are data latch chips between CPU and Agnus that insulates CPU side and chipset side of bus). Only second DMA slot is "used" for CPU data transfer. And if second slot is required for DMA, Gary tells CPU that memory is not ready ("simulated" memory wait state), please wait..

From CPU point of view memory access looked normal (possibly very long in worst case..) 68000 memory access where the CPU was in control of the access cycle, from Agnus point of view CPU was tricked

AFAIK all Amigas have same design, only way to have fast CPU memory accesses is to have local fast ram. A3000 and AGA implemented 32-bit wide CPU chip memory access.