68040 memory access

[phx]

Most 68k CPUs are faster when using a PC relative addressing mode to access memory, instead of an absolute 32bit address. Is it also true for the 68040? I heard it is different in this aspect. Can somebody confirm?

[matthey]

Originally Posted by phx

Most 68k CPUs are faster when using a PC relative addressing mode to access memory, instead of an absolute 32bit address. Is it also true for the 68040? I heard it is different in this aspect. Can somebody confirm?

Most 68k CPUs are faster when fetching smaller instructions giving instructions using PC relative addressing more of a performance advantage. The 68040 is an exception. There is less work to do for absolute addressing so these instructions are often faster than PC relative addressing on the 68040.

jmp (d16,PC)
1) sign extend d16 to d32
2) PC = PC + d32

jmp (xxx).W
1) sign extend (xxx).W to (xxx).L
2) PC = (xxx).L

jmp (xxx).L
1) PC = (xxx).L

It looks like the 68040 is able to do the sign extension for free in the case of (xxx).W vs (xxx).L as there is no timing difference (sign extension is a cheap operation). The EA calc cost of (d16,PC) is 3 cycles where (xxx).W and (xxx).L are 1 cycle. With no penalty for fetching the longer instructions, the 68040 is often faster using absolute addressing. An exception is the Bcc instruction which implicitly uses PC relative addressing and appears to have optimizations which make it faster than using (d16,PC). There can be an ICache performance penalty to larger instructions so the shorter code is usually preferable. Highly optimized 68040 specific code can can be quite large and you would probably want to look up timings in the MC68040UM.

[a/b]

Yeah, PC relative modes are slower on 040 (slower EA calc stage). Assuming extra code size due to absolute EAs won't screw up the cache.

Here are some speed test results I did on my A4000/040 long time ago (1000 repeats, code/raster_time/avg_cycles), not many PC relatives but it shows that absolute addressing is as fast as it gets:

	lea	(a0),a1		; 1112	1
	lea	(d.w,a0),a1	; 2391	2
	lea	(d.b,a0,d0.*),a1 ; 4954	4
	lea	(d.w,pc),a0	; 4954	4
	lea	(d.b,pc,d0.*),a0 ; 6232	5
	lea	($1234).w,a0	; 1112	1
	lea	($12345678),a0	; 1112	1
	move.	d0,d1		; 1112	1
	move.	a0,d0		; 1112	1
	move.	(a0),d0		; 1112	1
	move.	(d.w,a0),d0	; 1112	1
	move.	#,d0		; 1112	1
	move.	($12345678),d0	; 1159	1
	move.	d0,($12345678)	; 1141	1
	movea.w	d0,a0		; 3528	3
	movea.l	d0,a0		; 1767	1.5
	movea.	a0,a1		; 1112	1
	movea.	a0,($12345678)	; 1141	1
	movea.w	(a0),a1		; 3533	3
	movea.l	(a0),a1		; 2254	2
	movea.	#,a0		; 1112	1

[phx]

Thanks all! The bad performance with PC-relative modes is really surprising.
And the 060 changed that again? So PC-relative modes have at least no disadvantage there?

[matthey]

Originally Posted by phx

Thanks all! The bad performance with PC-relative modes is really surprising.
And the 060 changed that again? So PC-relative modes have at least no disadvantage there?

Yes.

Originally Posted by MC68060UM

68060 EA Calc times

Dn Data Register Direct 0(0/0)
An Address Register Direct 0(0/0)
(An) Address Register Indirect 0(0/0)
(An)+ Address Register Indirect with Postincrement 0(0/0)
–(An) Address Register Indirect with Predecrement 0(0/0)
(d16,An) Address Register Indirect with Displacement 0(0/0)
(d8,An,Xi*SF) Address Register Indirect with Index and Byte Displacement 0(0/0)
(bd,An,Xi*SF) Address Register Indirect with Index and Base (16-, 32-bit) Displacement 1(0/0)
([bd,An,Xn],od) Memory Indirect Preindexed Mode 3(1/0)
([bd,An],Xn,od) Memory Indirect Postindexed Mode 3(1/0)
(xxx).W Absolute Short 0(0/0)
(xxx).L Absolute Long 0(0/0)
(d16,PC) Program Counter with Displacement 0(0/0)
(d8,PC,Xi*SF) Program Counter with Index and Byte Displacement 0(0/0)
(bd,PC,Xi*SF) Program Counter with Index and Base (16-, 32-bit) Displacement 1(0/0)
#<data> Immediate 0(0/0)
([bd,PC,Xn],od) Program Counter Memory Indirect Preindexed Mode 3(1/0)
([bd,PC],Xn,od) Program Counter Memory Indirect Postindexed Mode 3(1/0)

The 68060 pipeline length is longer which makes it easier to hide the EA calc cost. It is an impressive design to make most of these addressing modes free which encourages the smallest code and most efficient use of the ICaches. The instruction fetch penalty is back also with a small fetch shared by 2 pipes (the fetch is only 4 bytes/cycle but buffered so usually isn't too much of a bottleneck). Code compiled for the 68030 and scheduled for the 68060 runs very well on the 68060 if the instructions missing from hardware are avoided. Code can use these more powerful addressing modes more when optimizing specifically for the 68060 but care must be taken to keep the instructions short. The memory double indirect modes reduce instruction scheduling opportunities so should be used with care.