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Old 11 January 2015, 00:32   #1
ovale
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Blithog behavior

Hello,

The HRM says "If DMAF_BLITHOG is a 0, the DMA manager will monitor the 68000 cycle requests. If the 68000 is unsatisfied for three consecutive memory cycles, the blitter will release the bus for one cycle."

Assuming
5 bitplanes are active
a blit with 4 channels is active (no idle cycles)
BLITHOG is zero
Code in chipram

Then, how a movem.w to chip ram is sequenced?

Is this sequence correct?

vvvbvrvbvvvrvbvbvvvwvbvbvvvw...
v = video DMA
b = Blitter DMA
r = CPU read access
w = CPU write access

I ask because this behavior seems really penalizing the 68k compared to the Blitter.

Thanks
Ovale
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Old 11 January 2015, 03:46   #2
mc6809e
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Ideally the blitter would always yield to the CPU since the CPU if need be can always be stopped with a STOP instruction.

Perhaps there was some technical reason for the three cycle rule. At least two cycles seem to be required since the CPU asserts *AS around the time Agnus is setting things up for a transfer on the next cycle and the next cycle itself must complete before letting the CPU back in.

Still, I don't think the CPU is too heavily penalized.
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Old 11 January 2015, 12:52   #3
Toni Wilen
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I checked using my logic analyzer and it seems to always repeat same sequence after it has "synced":

B4C2B351 C4B2B351 C4B2B351 C4B2B351

(B = blitter, C = CPU, number = plane)

Logic which I have used in emulation seems to still work: if CPU has waited at least 4 cycles: give any future blitter cycle to CPU. Reset counter when CPU gets any free cycle.
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Old 11 January 2015, 16:05   #4
ovale
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Thanks for the answers.

Assuming, this time, the code is in fast ram. The 68k will continue to get 3 wait states (6 DMA cycle) for every write.

Is there any way to use fast ram and prefetch to gain better parallelism between plain 68k and Blitter when copying data to chipram?

I guess no, but I'm not an expert so better to ask
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Old 12 January 2015, 07:46   #5
mc6809e
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Intentionally using some of the slower channel combinations might improve concurrency in some situations and improve overall speed.

For example, a B->D copy has one idle cycle. These idle cycles combined with BLIT_HOG turned off will allow the CPU to touch chipram five times for every six blitter accesses during bitplane fetch of a five bitplane display.

(BTW, technically every DMA cycle that blocks the CPU introduces two waits.)
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Old 12 January 2015, 09:05   #6
ovale
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Yes, I thought to Blitter idle cycles too but I hoped for some 68k trick.<br />
<br />
By the way, is there any way to obtain idle cycles when using all the 4 Blitter channels?<br />
<br />
Thanks

Edit: I mean, I hoped that some of the techniques used in c2p routines could be used in this case too

Last edited by ovale; 12 January 2015 at 18:40.
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