Hardware Idea: Making use of microcode to improve 68k emulation performance

[HenryCase]

Hi all,

I've just found out a little bit about how CPU microcode works, and had what could possibly be a braindead idea to use it to improve 68k emulation performance. I should make it clear I'm fully aware I'm out of my depth here, so what I'm about to say could be complete baloney.

Idea came after reading this ReactOS newsletter:
http://www.reactos.org/en/newsletter_89.html

Quoted text in particular:

Most programmers understand that processors conform to an Instruction Set Architecture, specifying what instructions and operations the processor can execute. What many people are unaware of or do not think much about is the fact that most processors do not directly execute instructions as specified by the ISA. Instead, there is a lower level of commands known as microcodes that control the operation of the processor to produce output conforming the an ISA. These microcodes are for the most part completely undocumented as AMD and Intel treat them as trade secrets. Modern CPU designs however are extremely complex and hardware bugs can slip in which do not correctly obey a microcode. Fixing such an issue in hardware would require changing the design, but modern CPUs can actually be patched with updated microcode to compensate for these errors.

So what I'm getting from this is that the functions in the x86 ISA are not written directly to the silicon, but instead implemented in microcode, which allows for flexibility in routing around hardware bugs, and optimising performance. This also ties in with things I've heard about modern x86 CPUs, that at their core the architecture is more RISC-like, and the CISC x86 design is built on top of this.

My main question is this: To what level could you make a modern 'x86' CPU behave like a 68k CPU through use of microcode? For example, if you had a multicore machine, could you make one of those cores execute instructions from the 68k ISA without requiring use of the x86 ISA for translation?

If implementing the 68k ISA in microcode on an x86 CPU wasn't possible, could microcode be used to optimise 68k emulation so that 68k instruction execution took fewer CPU cycles?

Your thoughts please. Thank you.

P.S. If anyone has any good introductory articles about microcode they could link to, please share them so I/we can learn more. Thanks.

[jimbob]

Well I'm probably even more out my depth than you, but I always thought that microcode was completely internal to the cpu, externally you still have to use the "exposed" instruction set.

From your quote, it sounds like this might not be the case, but you would have to convince AMD or Intel to create 68k emulation microcode for you, interesting idea, I wish I knew more about this stuff but it is generally over my head.

[HenryCase]

Originally Posted by jimbob

Well I'm probably even more out my depth than you, but I always thought that microcode was completely internal to the cpu, externally you still have to use the "exposed" instruction set.

From your quote, it sounds like this might not be the case, but you would have to convince AMD or Intel to create 68k emulation microcode for you, interesting idea, I wish I knew more about this stuff but it is generally over my head.

Thanks for your reply jimbob. I'm glad you think the idea is interesting, even if neither of us know whether it's possible to implement.

With regards to convincing AMD or Intel to create 68k emulation microcode for you, certainly the secretive nature of microcode is a barrier here, but perhaps it would be possible to reverse engineer the microcode design to be able to implement a sort of 'microcode compiler', i.e. take a fixed design like the 68060 ISA and use a tool to translate it to the microcode of the CPU you're using. To start accumulating the knowledge needed to do this, could disassemble the microcode patches that Intel and AMD provide in binary form, to get clues about how to write microcode, and go from there.

I'm not saying it'll be an easy thing to do, and I don't even know if it would be possible, but it would be good to know if such a possibility existed.

More information definitely welcome!

[Amiga1992]

I will talk totally out of depth here hehehe.
What would the advantage of this really be? I think the computers we have today emulate the Amiga really fast. What would exactly be the application of this?

Also, I always deemed the hardest part of getting an emulated Amiga going, be it by hardware or software, is the chipset.

[HenryCase]

Originally Posted by Akira

I will talk totally out of depth here hehehe.
What would the advantage of this really be? I think the computers we have today emulate the Amiga really fast. What would exactly be the application of this?

Imagine a 68k CPU that could run at close to current x86 speeds, and what you could do with this power. That's the potential benefit here. I say 'close to' as it's not clear what radically altering the ISA would do to the raw performance.

HD video, high speed 3D rendering, super fast compile times, pro-level audio production, etc... (software permitting). Basically it'd bring 68k performance bang up to date.

If such a scheme worked, it'd also have benefits for PPC Amiga operating systems too.

Also, I always deemed the hardest part of getting an emulated Amiga going, be it by hardware or software, is the chipset.

I've never written an Amiga emulator, so I couldn't say. On the subject of Amiga chipset emulation, there was talk in the past year or so of using a GPU to emulate the Amiga chipset functions, which is probably a fairly good approach to accelerating the performance. No code demonstrating this has been released yet though, AFAIK.

[HenryCase]

I've done a bit more digging. It seems that microcode compilers are known as microassemblers (or meta-assemblers). Issue being that the ones that support modern x86 CPUs appear to be proprietary and not available to the general public. More information here:
http://en.wikipedia.org/wiki/Microassembler

Here's a list of Intel CPUs that support microcode updates:
https://wiki.archlinux.org/index.php...rocode_updates

Also, from that same wiki page, it appears it's possible to update microcode at runtime, on Linux at least.

If we had an open-source microassembler we may be in business here. Even if it only supported a single x86 CPU it would still be useful, as you could (potentially) use that CPU to create a new 68k accelerator for classic Amigas (or any other device that used a 68k CPU). This is the only existing open-source microassembler/meta-assembler project I've found so far, no idea what it supports:
http://sourceforge.net/projects/metalasm/