English Amiga Board


Go Back   English Amiga Board > Coders > Coders. Asm / Hardware

 
 
Thread Tools
Old 29 January 2020, 19:59   #1
DanScott
Lemon. / Core Design

DanScott's Avatar
 
Join Date: Mar 2016
Location: Sunny Bournemouth, UK
Posts: 587
Using the disk DMA to clear memory?

Is this possible? Saw this mentioned in a FB thread... anyone done this?
DanScott is offline  
Old 29 January 2020, 20:48   #2
ross
Per aspera ad astra

ross's Avatar
 
Join Date: Mar 2017
Location: Crossing the Rubicon
Age: 49
Posts: 2,472
Quote:
Originally Posted by DanScott View Post
Is this possible? Saw this mentioned in a FB thread... anyone done this?
Even if possible, isn't it very slow? (only 3 DMA slot /line..).
Or is it just a proof of concept?
ross is offline  
Old 29 January 2020, 21:30   #3
DanScott
Lemon. / Core Design

DanScott's Avatar
 
Join Date: Mar 2016
Location: Sunny Bournemouth, UK
Posts: 587
Someone said they had used it, and it had help save some cycles...
DanScott is offline  
Old 29 January 2020, 21:54   #4
ross
Per aspera ad astra

ross's Avatar
 
Join Date: Mar 2017
Location: Crossing the Rubicon
Age: 49
Posts: 2,472


Let's do two calculations:
you can clear 1878byte/frame, so for a simple 320x256 single plane you need 10240/1878=5,45 50Hz frames to do it..
With the blitter you need only few video lines for the same bitplane (using also the same DMA slots of the unused DISK DMA).
I dont see any advantage.

The only (negligible) use could be to clear small areas of memory in a deferred way from the blitter and the processor.
Nothing striking.

EDIT: anyway for a DISK DMA start you need a 'signal' from Paula and the MFM bit stuffing is at max 2ns/bit, so this 'virtual' figure is smaller..
all this for me has no logical use (even if it were possible)

Last edited by ross; 29 January 2020 at 22:28.
ross is offline  
Old 30 January 2020, 04:41   #5
FSizzle
Registered User

 
Join Date: Nov 2017
Location: Los Angeles
Posts: 36
When clearing, using one channel only, the blitter cannot write during every available DMA slot. In the same way that you can clear memory on the 68000 more quickly by using the blitter and CPU simultaneously, couldn't you use the disk DMA and blitter simultaneously, accelerating the clear with the disk DMA slightly?

I'm not sure how you'd make the disk DMA write the desired data though.
FSizzle is offline  
Old 30 January 2020, 06:18   #6
Thomas Richter
Registered User
 
Join Date: Jan 2019
Location: Germany
Posts: 348
Quote:
Originally Posted by DanScott View Post
Is this possible? Saw this mentioned in a FB thread... anyone done this?
Yes, as long as this is chip memory. Yes. And the function for that is in the graphics.library, named "BltClear()".
Thomas Richter is offline  
Old 30 January 2020, 06:44   #7
FSizzle
Registered User

 
Join Date: Nov 2017
Location: Los Angeles
Posts: 36
Quote:
And the function for that is in the graphics.library, named "BltClear()".
That function uses the blitter. OP is asking about using disk DMA.
FSizzle is offline  
Old 30 January 2020, 07:30   #8
ross
Per aspera ad astra

ross's Avatar
 
Join Date: Mar 2017
Location: Crossing the Rubicon
Age: 49
Posts: 2,472
Quote:
Originally Posted by FSizzle View Post
When clearing, using one channel only, the blitter cannot write during every available DMA slot. In the same way that you can clear memory on the 68000 more quickly by using the blitter and CPU simultaneously, couldn't you use the disk DMA and blitter simultaneously, accelerating the clear with the disk DMA slightly?

I'm not sure how you'd make the disk DMA write the desired data though.
When i want a quick routine to clear the chip memory i always use the blitter and the CPU together, so that all access cycles to chip ram are used (0 minterm and movem).
So it makes no sense to use the DISK DMA, in any case its allocated DMA slot cycles would be used by the blitter.
ross is offline  
Old 30 January 2020, 09:02   #9
Thomas Richter
Registered User
 
Join Date: Jan 2019
Location: Germany
Posts: 348
Quote:
Originally Posted by FSizzle View Post
That function uses the blitter. OP is asking about using disk DMA.
Oh, I'm sorry. Concerning disk-DMA: How could one ensure that the input data at Paula is 0, which is necessary for cleaning?
Thomas Richter is offline  
Old 30 January 2020, 09:39   #10
meynaf
son of 68k
meynaf's Avatar
 
Join Date: Nov 2007
Location: Lyon / France
Age: 47
Posts: 3,701
Quote:
Originally Posted by ross View Post
So it makes no sense to use the DISK DMA, in any case its allocated DMA slot cycles would be used by the blitter.
Using the blitter may slow the cpu down. But as disk dma slots are allocated regardless if they are used or not, there may be some interest in having them do something basically for free.


Quote:
Originally Posted by Thomas Richter View Post
Concerning disk-DMA: How could one ensure that the input data at Paula is 0, which is necessary for cleaning?
By writing to DSKDAT maybe ?
meynaf is online now  
Old 30 January 2020, 10:18   #11
ross
Per aspera ad astra

ross's Avatar
 
Join Date: Mar 2017
Location: Crossing the Rubicon
Age: 49
Posts: 2,472
Quote:
Originally Posted by meynaf View Post
Using the blitter may slow the cpu down. But as disk dma slots are allocated regardless if they are used or not, there may be some interest in having them do something basically for free.
This is not completely right.
Yes that blitter can slow down the CPU, but it can use every free cycle (as the CPU), that in this specific case could be also DISK DMA cycles.

So these cycles "allocated regardless if they are used or not" are usable/used by the blitter/CPU during the clear operation

As I've written, the only (negligible) use could be to clear small areas of memory in a deferred way from the blitter and the processor (but not 'instead').

Last edited by ross; 30 January 2020 at 12:38. Reason: added CPU/blitter pair, not only blitter
ross is offline  
Old 30 January 2020, 10:46   #12
Toni Wilen
WinUAE developer
 
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 45
Posts: 23,668
If audio or disk or any DMA slot is not used by higher priority Agnus DMA channel, it is always usable by blitter or CPU (if blitter or CPU needs it).

Allocation is dynamic, unused DMA slots are never unavailable for blitter or CPU.
Toni Wilen is offline  
Old 30 January 2020, 11:22   #13
ross
Per aspera ad astra

ross's Avatar
 
Join Date: Mar 2017
Location: Crossing the Rubicon
Age: 49
Posts: 2,472
Quote:
Originally Posted by Toni Wilen View Post
If audio or disk or any DMA slot is not used by higher priority Agnus DMA channel, it is always usable by blitter or CPU (if blitter or CPU needs it).

Allocation is dynamic, unused DMA slots are never unavailable for blitter or CPU.
Toni is totally right here

Last edited by ross; 30 January 2020 at 12:35. Reason: master Toni :D
ross is offline  
Old 30 January 2020, 11:28   #14
roondar
Registered User

 
Join Date: Jul 2015
Location: The Netherlands
Posts: 1,725
Quote:
Originally Posted by ross View Post
Toni, in this case only by blitter because CPU cannot access chip memory during slots allocated for AUDIO or DISK DMA.
Of course different for other Agnus DMA channels.
I thought if disk DMA or audio DMA is in use then neither Blitter nor CPU can access any cycles the disk or audio DMA requires*?

But if there are free disk/audio "slots" then surely both the CPU and Blitter could access them?
Edit: assuming the CPU manages to get aligned to the correct slots to do so, obviously. It'll still only access memory every other cycle at best.

*) that is, not cycles during which disk/audio DMA are running but idle, but cycles where disk or audio DMA actually needs to access memory for that particular slot.

Last edited by roondar; 30 January 2020 at 11:38.
roondar is offline  
Old 30 January 2020, 11:44   #15
ross
Per aspera ad astra

ross's Avatar
 
Join Date: Mar 2017
Location: Crossing the Rubicon
Age: 49
Posts: 2,472
Quote:
Originally Posted by roondar View Post
I thought if disk DMA or audio DMA is in use then neither Blitter nor CPU can access any cycles the disk or audio DMA requires*?
Partially yes (see next point), only video DMA can 'steal' cycles allocated for 'Paula''s requests to Agnus (and is not a good thing, because can steal also memory refresh slots).
EDIT: anyway this is not simple, i think only on AGA you can 'overrun' bitplane DMA up to DISK/AUDIO slots but sure OCS/ECS for refresh slots.

Quote:
But if there are free disk/audio "slots" then surely both the CPU and Blitter could access them?
Edit: assuming the CPU manages to get aligned to the correct slots to do so, obviously. It'll still only access memory every other cycle at best.
EDIT2: yep, your edit is right

Last edited by ross; 30 January 2020 at 12:53.
ross is offline  
Old 30 January 2020, 11:57   #16
roondar
Registered User

 
Join Date: Jul 2015
Location: The Netherlands
Posts: 1,725
Quote:
Originally Posted by ross View Post
P
Your edit is the focal point.
CPU can access only every other cycle at best, not these for AUDIO or DISK DMA, that can be instead used by blitter.
Just to be complete here and as I understand it:

If the CPU gets "misaligned" somehow at the start of a scanline, it will use all the AUDIO/DISK DMA channels slots (and sprite, etc) that are available until it's forced back into alignment. It definitely won't make much of a practical difference and often such misalignment is very temporary, but it's certainly theoretically possible for the CPU to be so aligned for all of those cycles in a scanline.

If this understanding is wrong, well, I'd love to learn

-----
On the topic of clearing with disk DMA and it's usefulness: thinking about this a bit more, I can see a "kind of, maybe" use-case here. Now, this definitely won't improve performance, but might still be useful in some scenarios.

You could effectively use this as a sort of "fire-and-forget" memory clear that just does it's thing while rest of the code gets run for the frame. So for instance, you could call disk DMA to clear a small section of memory you need to use next frame, while the rest of the code goes on doing other stuff with the Blitter or CPU. Not sure how useful this is, but it's still perhaps interesting.
roondar is offline  
Old 30 January 2020, 12:32   #17
ross
Per aspera ad astra

ross's Avatar
 
Join Date: Mar 2017
Location: Crossing the Rubicon
Age: 49
Posts: 2,472
Quote:
Originally Posted by roondar View Post
Just to be complete here and as I understand it:

If the CPU gets "misaligned" somehow at the start of a scanline, it will use all the AUDIO/DISK DMA channels slots (and sprite, etc) that are available until it's forced back into alignment. It definitely won't make much of a practical difference and often such misalignment is very temporary, but it's certainly theoretically possible for the CPU to be so aligned for all of those cycles in a scanline.

If this understanding is wrong, well, I'd love to learn
argh, you are right! CPU can misalign and use also these cycles! (the resulting effect does not change, but this specificity exists)
EDIT:
I'll edit my previous message adding CPU more than blitter access possibility on these DMA slots (Toni is always right )

Quote:
On the topic of clearing with disk DMA and it's usefulness: thinking about this a bit more, I can see a "kind of, maybe" use-case here. Now, this definitely won't improve performance, but might still be useful in some scenarios.

You could effectively use this as a sort of "fire-and-forget" memory clear that just does it's thing while rest of the code gets run for the frame. So for instance, you could call disk DMA to clear a small section of memory you need to use next frame, while the rest of the code goes on doing other stuff with the Blitter or CPU. Not sure how useful this is, but it's still perhaps interesting.
And this is my mentioned 'deferred' use case

Last edited by ross; 30 January 2020 at 13:01.
ross is offline  
Old 30 January 2020, 14:02   #18
Toni Wilen
WinUAE developer
 
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 45
Posts: 23,668
Quote:
Originally Posted by ross View Post
argh, you are right! CPU can misalign and use also these cycles! (the resulting effect does not change, but this specificity exists)
EDIT:
I'll edit my previous message adding CPU more than blitter access possibility on these DMA slots (Toni is always right )
Not being able to use and not requesting the free cycle are in my opinion totally different things

There are also instructions that have non 4 divisible cycle counts and long instructions like MUL and DIV.
Toni Wilen is offline  
Old 30 January 2020, 14:57   #19
ross
Per aspera ad astra

ross's Avatar
 
Join Date: Mar 2017
Location: Crossing the Rubicon
Age: 49
Posts: 2,472
Quote:
Originally Posted by Toni Wilen View Post
Not being able to use and not requesting the free cycle are in my opinion totally different things

There are also instructions that have non 4 divisible cycle counts and long instructions like MUL and DIV.


I've written a little test prog with unrolled movem series interleaved by a 6 cycles lsr d0,d0 (d0=0) and in VisualDMA debugger the effect is pretty visible.
ross is offline  
Old 30 January 2020, 16:47   #20
FSizzle
Registered User

 
Join Date: Nov 2017
Location: Los Angeles
Posts: 36
This post asks:

Can you clear memory using disk DMA?

Which is a fascinating question to me because it's not one I heard before.

Assuming it's possible, the implicit follow up question is:

Is there a situation that is useful or gives some benefit?

I can think of a situation in which it could be a performance enhancement and not just a curiosity. I tried to allude to this before, but didn't explain it very well (or really at all) so let me try again:

Let's say you have the following situation:
- CPU is not using the chip RAM bus much, or at all (doing expensive internal operations or running out of fastram)
- you want to clear a buffer

If you use the Blitter, in D channel mode as normal, you cannot utilize every chipram access cycle due to how the blitter works, so your bus access looks like:

Code:
-B-B-B-B-B-B-B-B-B-B-B-B...

- = Idle    B = Blitter
If you were to use the disk DMA, it looks like this:
Code:
-D-D-D-------------...

- = Idle    D = Disk
Now if you combine the two, I think you will get this:

Code:
-DBDBDB-B-B-B-B-B-B-B-B-...

- = Idle    B = Blitter    D = Disk
i.e. on the first conflicting access between the Disk and Blitter, the Disk will have priority, resulting in delaying the blitter. From that point on there should be no contention.

If I'm right about this behavior, you now have ~1.8 KiB of extra clearing bandwidth per frame.

Naturally you could replace the blitter clear operation with some other operation that also cannot saturate the bus as well (like an A->D copy of for example) and similarly be able to utilize some extra chip ram access slots.

I could be wrong about the timing, or the effect the contention would have on delaying the blitter. It could be proven either way with a small piece of test code, but I bet Toni also just knows
FSizzle is offline  
 


Currently Active Users Viewing This Thread: 1 (0 members and 1 guests)
 
Thread Tools

Similar Threads
Thread Thread Starter Forum Replies Last Post
A1200 CPU memory access speed (with DMA) roondar Coders. Asm / Hardware 38 23 July 2019 09:49
Glitchy sound when enabling Cycle exact DMA/Memory accesses SLC support.WinUAE 10 29 January 2018 15:03
Clear Plastic Floppy Disk Sleeves diablothe2nd Amiga scene 4 18 September 2012 08:54
Wanted: 5.25" Clear Plastic Disk Cases BarryB MarketPlace 7 29 December 2009 16:19
DMA memory to memory copy BlueAchenar Coders. General 14 22 January 2009 23:29

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off

Forum Jump


All times are GMT +2. The time now is 08:56.


Powered by vBulletin® Version 3.8.11
Copyright ©2000 - 2020, vBulletin Solutions Inc.
Page generated in 0.09381 seconds with 13 queries