flawless double buffering

[dalton]

When using a double buffered screen, you typically store the bitplane pointers in an intermediate buffer in memory and then copy them to the custom registers on vblank.

The problem with this approach is that sometimes vblank will occur while you are creating the intermediate buffer, so that it is inconsistent when copied to the custom regs causing the screen to flicker.

Is there some way of preventing vblank from occuring during a critical section of code? I dont think disabling it is an option, as that would cause the pointers not to be written. Ideally I would like to postpone it just a little

[Kalms]

You can accomplish this either by raising the IPL in SR, or by temporarily masking out the VERTB bit in INTENA.

If the vblank event occurs during this specific period of time, the VERTB bit will get set in INTREQ. Then, when you restore the IPL (or the VERTB bit in INTENA), the VERTB interrupt will immediately trigger.

So you won't miss any VERTB events by doing this. Note that if you have a custom level3 handler and support VERTB/BLIT/COPER, your lev3 handler should only acknowledge (clear) flags in INTREQ for exactly those handlers that you run. Don't always acknowledge VERTB|BLIT|COPER by default - then you will occasionally miss out on interrupts.

[dalton]

nice, thanks!