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Old 30 January 2020, 17:11   #21
Toni Wilen
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It does not work that way. Blitter idle cycles need free cycle. (But because blitter does not "use" it, it is also available for the CPU)
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Old 30 January 2020, 17:40   #22
ross
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Just tried in WinUAE at there is a funny collateral effect
Memory is immediately cleared for the whole DMA words requested.

Code:
DiskDMAClear
	lea	$dff000,a0
	move.w	#$7fff,d0
	move.w	d0,$9a(a0)
	move.w	d0,$96(a0)
	move.w	d0,$9e(a0)
	move.w	#$8100,$9e(a0)
	move.w	#$8210,$96(a0)
	moveq	#0,d0
	move.l	d0,$20(a0)
	move.w	#$bfff,$24(a0)
	move.w	#$bfff,$24(a0)
stp	bra.b	stp
Maybe even in a real machine!
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Old 31 January 2020, 07:48   #23
FSizzle
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Quote:
Originally Posted by Toni Wilen View Post
It does not work that way. Blitter idle cycles need free cycle. (But because blitter does not "use" it, it is also available for the CPU)

Thanks Toni.


That behavior is a little surprising. I wonder why it is this way. No doubt there is some hardware reason.
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Old 31 January 2020, 12:09   #24
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Quote:
Originally Posted by FSizzle View Post
Naturally you could replace the blitter clear operation with some other operation that also cannot saturate the bus as well (like an A->D copy of for example) and similarly be able to utilize some extra chip ram access slots.
A->D copy saturate the bus (of course with BLITPRI active).
Only A->D fill mode has a idle cycle.


Quote:
Originally Posted by FSizzle View Post
That behavior is a little surprising. I wonder why it is this way. No doubt there is some hardware reason.
Maybe something internal to simplify Agnus' DMA arbitration?
Probably Toni got an idea of why. (Agnus really need a decap )

Yes, this behavior change a bit your way to thinking about blitter usage and change how you could use/optimize it.
However, the fact that these cycles can be used by the CPU allows you to take advantage, in many cases, of a better operations overlapping.
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Old 31 January 2020, 16:45   #25
Toni Wilen
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Quote:
Originally Posted by ross View Post
Just tried in WinUAE at there is a funny collateral effect
Memory is immediately cleared for the whole DMA words requested.
If disk DMA was started but no drives were selected, it always used turbo mode, probably happened when Amax drive support was added.

Quote:
Originally Posted by ross View Post
Maybe something internal to simplify Agnus' DMA arbitration?
Probably Toni got an idea of why. (Agnus really need a decap )
My guess is that at least some blitter idle cycles do some internal operations that require use of Agnus internal buses/adder/something and improving arbitration was too complex. (I am almost certain Agnus has internal pipelining and at least bitplane DMA decisions are done few cycles before cycle actually happens)
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Old 31 January 2020, 17:49   #26
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Quote:
Originally Posted by Toni Wilen View Post
If disk DMA was started but no drives were selected, it always used turbo mode, probably happened when Amax drive support was added.
Works now, thanks , so my stupid code can be taken as a starting point for some tests.

Only one warning for those who want to try: first DMA word written contain junk data (I suppose some residual from Paula' internal raw data shifter).
And no, writing to DSKDAT to try to zero it do not work, I suppose because the register is a buffer for an incoming full DMA word.
And also no, try to sync to a WORDSYNC=0 (or MSBSYNC) do not work.

EDIT: at least this in WinUAE, no idea on a real machine .

---

Actually there is an Agnus decap:
https://upload.wikimedia.org/wikiped..._top_metal.jpg
but I don't know how useful it can be

Last edited by ross; 31 January 2020 at 18:16.
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Old 01 February 2020, 14:05   #27
Toni Wilen
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Garbage at the beginning does not happen when using real A500 (It is just a side-effect of nothing being selected)

If WORDSYNC is enabled, it takes 1-2 seconds before zeros are written to RAM. So apparently sync detector sees noise which sooner or later matches and DMA starts. But why does DMA only write zeros to RAM?

If disk drive is disconnected, there is no delay, zero writing starts immediately. (Read line pulled down/up vs floating side-effect?)

Paula internal PLL doing something weird when it does not see any pulses?
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Old 01 February 2020, 17:28   #28
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Quote:
Originally Posted by Toni Wilen View Post
If WORDSYNC is enabled, it takes 1-2 seconds before zeros are written to RAM. So apparently sync detector sees noise which sooner or later matches and DMA starts. But why does DMA only write zeros to RAM?
Yes, this is weird..
What are the precise conditions? $7e=0 and no drive selection?

Quote:
If disk drive is disconnected, there is no delay, zero writing starts immediately. (Read line pulled down/up vs floating side-effect?)
This make sense. So a mandatory condition is the selection of a disconnected unit, which cannot be guaranteed, so the code may not work in some configurations.

Quote:
Paula internal PLL doing something weird when it does not see any pulses?
Any idea how Paula (digital) PLL works?
A time counter for when a flux change (incoming 1 bit) is detected and a CCK-shift (in case) from the default 7*CCK spacing?
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Old 01 February 2020, 20:41   #29
Toni Wilen
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Quote:
Originally Posted by ross View Post
Yes, this is weird..
What are the precise conditions? $7e=0 and no drive selection?
Few bits of random data was injected to bit buffer to simulate motor start delays/step to other track/PLL not yet in sync etc.. And it was injected even when no floppy drive was selected.

Quote:
Any idea how Paula (digital) PLL works?
A time counter for when a flux change (incoming 1 bit) is detected and a CCK-shift (in case) from the default 7*CCK spacing?
No.
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Old 01 February 2020, 21:39   #30
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No, sorry, I'm referring the values/settings you have used in a real machine for the results in quoted part [DSKSYNC value, drive selection (in case), motor (in case)..]:
Quote:
Originally Posted by Toni Wilen View Post
If WORDSYNC is enabled, it takes 1-2 seconds before zeros are written to RAM. So apparently sync detector sees noise which sooner or later matches and DMA starts. But why does DMA only write zeros to RAM?
Thanks
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Old 01 February 2020, 22:11   #31
Toni Wilen
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I didn't touch any floppy CIA registers (so no floppy selected, no motor started etc..)

I only switched on and off WORDSYNC bit and removed internal drive.
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