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Old 21 March 2018, 16:27   #1
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CD32 Reset Line Stuck Low

I'm trying to repair a CD32 that has its reset line stuck low. I'm having a bit of trouble tracking down the culprit and the schematics (or my reading of them) aren't giving me any help.

In the reset section of the schematic I've got a diode leaking (D629) but the voltage out of U14 is ok (5V). I'm not sure if/when this ties in to the reset circuit as the schematic has it going to the button and then off to the keyboard connector. The schematic doesn't have any reset line connection for this circuit.

The input on U37 (Pin 10) is low, 0.0V and the output (Pin 8) is 0.2V. I can't see on the schematic where the 5V would be generated from the input side of the circuit (assuming that the reset is triggered by any of the chips pulling it temporarily low).

A quick diode check on U37 didn't point to a problem. I'm pretty sure I'm missing something obvious, maybe I've been looking at the schematic too long
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Old 21 March 2018, 16:35   #2
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Have you been in here: http://beta.amigapcb.org - makes the schematics a lot more accessible!
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Old 21 March 2018, 16:56   #3
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Thankyou! Those diagrams are amazing! That made finding the voltage input so much easier - it's coming through R951B and being pulled low by one of the chips it would seem.

Are there any common culprits? Lifting all of the main IC's will be a fairly serious undertaking, I guess I'm looking at U1 (CPU), U2 (Alice), U3 (Paula) and U5. If any of those chips are removed could I get a 'normal' reset lock that would complicate things?
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Old 21 March 2018, 22:56   #4
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The Reset signals are generally open collector, so are you sure the pull-up resistor is working? Perhaps measure resistance between 5V and the _RST pin on one of the chips, or even better, at pin 9 of TP2. It should be ~1K. If that resistor pack has failed, the main reset and all dependent reset signals will stay low.
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Old 22 March 2018, 02:09   #5
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Yeah it's got a 1k resistance from reset to 5V, everything so far appears normal in relation to the reset circuit (aside from it being held low).
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Old 24 March 2018, 18:06   #6
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Just investigating the cause of the reset line being held down further, the clock signals are all present though there's no CAS signal. The Processor Halt is ok (high), and there's nothing out of ROM Enable but I assume that would be normal in reset.

Should Alice generate the CAS signal even when in a reset state or could it be the cause?

Does anyone have any other suggestions for further diagnosis to narrow down the culprit?

edit. I also just noted a lack of a Data & Address Strobes, guessing these are a symptom and not a cause?

Last edited by Dipski; 24 March 2018 at 18:27.
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Old 25 March 2018, 10:18   #7
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I have no idea why the reset line would end up pulling the
keyboard clock signal low, or if it’s just a schematic error.
The Ricoh part in the reset circuit is known to fail.
Hasn’t happened here, but I’ve seen it a few times.
It looks as though if the schematic is correct, disconnecting
the output of the Ricoh part would take the whole button reset out of the picture, and leave KB clock pulled high.

Thinking some more, maybe the reset occurs when KB clock
is pulled low for a duration, since the operation of a keyboard would never call for a long pulse.
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Old 14 April 2018, 11:56   #8
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Thanks for the reply, I didn't quite follow initially.

I removed U14 (reset button control) which didn't have any effect, and I disconnected the output on U37 in the hope it was grounding the reset line, but it is remaining low on the input side.

Just to check my process, with the U37 output disconnected (pin 8) I should still see 5V on the reset line on the input side if there is no fault (pin 8)? Is the purpose of U37 to drive the expansion port reset line low when the system is in reset, and to prevent the opposite from occurring?

I guess I'm a little stuck on how to track down the problem from here - I'm not sure what to rule in or out, with little activity on the board and all clocks working it's hard to differentiate which signals (or lack thereof) are caused by the reset state, or if one of them is the cause.
  • Address strobe and data strobe are high (no activity)
  • Processor read/write is high (no activity)
  • Size_0 and Size_1 are high (no activity)
  • No activity on the address lines
  • D_sack_0 and D_sack 1 are high (no activity)
  • CPU_br is high (no activity)
  • CBR_bg has no activity sitting at 3.8V
  • Halt is high
  • Reset stuck low
  • ROM_en and ROM_ds have no activity

Incidentally the ROM has been checked and is working.

Could the CPU hold the reset down if there's a memory fault? Can the CPU hold the reset line down due to an internal fault? Can Alice, Paula, Akiko or Lisa drag the reset line down themselves (can it only be the CPU holding it down)?
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