02 July 2018, 21:43 | #21 |
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I don't really understand how this will simplify the design. Considering only the LoRes pixel clock, if this same as the CPU clock why can't this be used? Are they at different phases?
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02 July 2018, 22:20 | #22 |
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It can be different phase - you should check Gayle datasheet - there is waveforms provided to show all dependencies. Side to this my assumption is that you using video port not hooking wires to pins internally.
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02 July 2018, 22:41 | #23 | |
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What signals in the GAYLE data sheet are you referring to specifically? |
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03 July 2018, 00:38 | #24 | |
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Check page 10 - video clocks and phase relations between them. |
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03 July 2018, 10:40 | #25 |
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Thanks! Have you made something similar yourself? You appear to know quite a lot on this topic.
My PCBs arrived yesterday for my 68SEC000 accelerator so that will take priority (after family and work) and then I will circle back to this at some point. |
03 July 2018, 11:27 | #26 | |
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Progress is slow due other things with higher priority. I need to finish other things first so decided to shift effort on this - but if i can help then i will be happy to do so. |
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04 July 2018, 12:49 | #27 |
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Thanks. I will be sure to keep you in the loop when I pick it up again. I populated my 68SEC000 accelerator last night and I see about 15 bus cycles then the CPU /HALT is asserted. Something is fundamentally wrong so it might be while before I pick up on the LCD work again. If you are interested in this I can share the details of that also!
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06 July 2018, 17:18 | #28 | |
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If you face any problem then you should share details on forum - there is many people actively involved in Amiga HW project. |
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06 July 2018, 23:27 | #29 |
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I've got my other Thread hear;
http://eab.abime.net/showthread.php?t=89165 However, as it has taken soooooooo long I've lost critical mass! Nevertheless, I will not be defeated! |
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