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Old 19 May 2018, 21:05   #41
SpeedGeek
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** 10TH NEWS UPDATE **

v1.8 Released!
- Reworked the code to eliminate a serious (but seldom noticed) data transfer corruption bug for the case of multiple DMA drivers in the same system. Special Thanks to Ralph Babel for his excellent knowledge on this topic.

Last edited by SpeedGeek; 19 May 2018 at 21:18.
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Old 21 May 2018, 18:53   #42
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** 11TH NEWS UPDATE **

v1.9 Released!
- Fixed "D2 Register Not Preserved" coding bug in PreDMA.
Most DMA drivers don't seem to need it preserved but
Thanks to Cosmos for reporting it anyway. Moved PostDMA
Nest count code to user section of code. This eliminates
any calls to Supervisor when the count is more than 1.
v1.9BR Added new "Experimental" code which should allow only
DMA targeted 16MB blocks of Fast RAM to change to Write
Through mode. This "In Theory" allows the other 16MB
blocks to remain in Copyback mode. This can only benefit
"Big RAM" systems with 32MB+ of Fast RAM and ONLY when
these systems run apps which use the extra Fast RAM.
WARNING: Use at you own risk!

CACHEDMABENCH:
v1.0 - First release
v1.1 - Fixed address and size bugs in FC loop code which
could have affected the results.
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Old 23 May 2018, 22:18   #43
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A4000 - cyberstorm mk3 72mhz - 128mb fastram

Without Fastcache040

CacheDMAbench 1.1 ©SpeedGeek 2018
---------------------------------
Public memory CacheDMA FCs: 9500
Chip memory CacheDMA FCs..: 500
Total CDMA Function Calls.: 10000
Elapsed time Microseconds.: 393637

With Fastcache040

CacheDMAbench 1.1 ©SpeedGeek 2018
---------------------------------
Public memory CacheDMA FCs: 9500
Chip memory CacheDMA FCs..: 500
Total CDMA Function Calls.: 10000
Elapsed time Microseconds.: 113858
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Old 15 October 2018, 02:35   #44
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Quote:
Originally Posted by SpeedGeek View Post
FixMapP5 1.2 ©SpeedGeek 2018 (MMU Handler ©Michael Sinz 2001)
Well, running this tool only changes $F00000-$F80FFF to writethrough. The rest of ROM(copyback) and all of chipmem(imprecise) is unchanged.
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Old 15 October 2018, 16:59   #45
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Quote:
Originally Posted by NorthWay View Post
Well, running this tool only changes $F00000-$F80FFF to writethrough. The rest of ROM(copyback) and all of chipmem(imprecise) is unchanged.
That's interesting. Please specify your P5 library version and accelerator card. FixMapP5 only works after the P5 library is installed and it's possible that the firmware modifies the MMU mapping after FixMapP5 has been run (But I can't verify this on my A3660 system).
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Old 15 October 2018, 21:07   #46
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CS MK1 with 68060.library 46.15.

EDIT: And I use 'mmulist' by Michael van Elst(sp?) to look at the result.
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Old 16 October 2018, 17:54   #47
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With the 68060.library 46.15 I get the following (before and after FixMapP5) results:

Before:
Code:
Current 68060 MMU table setup:
$00000000-$00000FFF -> $07071000: Local  User  Valid   Read/Write Copyback
$00001000-$00003FFF -> $0705A000: Local  User  Valid   Read/Write Precise   
$00004000-$001FFFFF -> $00004000: Local  User  Valid   Read/Write Nocache 
$00200000-$00BBFFFF -> $0705A000: Local  User  Valid   Read/Write Precise   
$00BC0000-$00BFFFFF -> $00BC0000: Local  User  Valid   Read/Write Precise   
$00C00000-$00D7FFFF -> $0705A000: Local  User  Valid   Read/Write Precise   
$00D80000-$00E7FFFF -> $00D80000: Local  User  Valid   Read/Write Precise   
$00E80000-$00EFFFFF -> $0705A000: Local  User  Valid   Read/Write Precise   
$00F00000-$00FFFFFF -> $00F00000: Local  User  Valid   Read/Write Copyback
$01000000-$06FFFFFF -> $0705A000: Local  User  Valid   Read/Write Precise   
$07000000-$07059FFF -> $07000000: Local  User  Valid   Read/Write Copyback
$0705A000-$0705AFFF -> $0705A000: Local  User  Valid   Read/Write Nocache 
$0705B000-$07064FFF -> $0705B000: Local  User  Valid   Read/Write Precise   
$07065000-$07067FFF -> $07065000: Local  User  Valid   Read/Write Copyback
$07068000-$07068FFF -> $07068000: Local  User  Valid   Read/Write Precise   
$07069000-$07FFFFFF -> $07069000: Local  User  Valid   Read/Write Copyback
$08000000-$FFFF7FFF -> $0705A000: Local  User  Valid   Read/Write Precise   
$FFFF8000-$FFFFFFFF -> $07069000: Local  User  Valid   Read/Write Copyback
After:
Code:
Current 68060 MMU table setup:
$00000000-$00000FFF -> $07071000: Local  User  Valid   Read/Write Copyback
$00001000-$00003FFF -> $00202000: Local  User  Valid   Read/Write Precise   
$00004000-$001FFFFF -> $00004000: Local  User  Valid   Read/Write Precise   
$00200000-$00BBFFFF -> $00202000: Local  User  Valid   Read/Write Precise   
$00BC0000-$00BFFFFF -> $00BC0000: Local  User  Valid   Read/Write Precise   
$00C00000-$00D7FFFF -> $00202000: Local  User  Valid   Read/Write Precise   
$00D80000-$00E7FFFF -> $00D80000: Local  User  Valid   Read/Write Precise   
$00E80000-$00EFFFFF -> $00202000: Local  User  Valid   Read/Write Precise   
$00F00000-$00FFFFFF -> $00F00000: Local  User  Valid   Read/Write Cache   
$01000000-$06FFFFFF -> $00202000: Local  User  Valid   Read/Write Precise   
$07000000-$07059FFF -> $07000000: Local  User  Valid   Read/Write Copyback
$0705A000-$0705AFFF -> $0705A000: Local  User  Valid   Read/Write Nocache 
$0705B000-$07064FFF -> $0705B000: Local  User  Valid   Read/Write Precise   
$07065000-$07067FFF -> $07065000: Local  User  Valid   Read/Write Copyback
$07068000-$07068FFF -> $07068000: Local  User  Valid   Read/Write Precise   
$07069000-$07FFFFFF -> $07069000: Local  User  Valid   Read/Write Copyback
$08000000-$FFFF7FFF -> $00202000: Local  User  Valid   Read/Write Precise   
$FFFF8000-$FFFFFFFF -> $07069000: Local  User  Valid   Read/Write Copyback
I use a modified version the Enforcer MMU tool (because MMUlist is annoyingly slow and long). It's certainly possible that the P5 software (Rom2Fast, SetCacheMode, CyberGuard, etc.) can change the MMU table setup after FixMapP5 so you may need to run it again if that's the case. Sorry, but the only permanent fix is to patch the P5 libraries.

P.S. The ROM mapping change to write-through is optional and won't affect system stability.

Last edited by SpeedGeek; 20 October 2018 at 16:50.
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Old 20 October 2018, 04:31   #48
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Quote:
Originally Posted by SpeedGeek View Post
With the 68060.library 46.15 I get the following (before and after FixMapP5) results:
So I fired up Resource to take a look, and I sit here wondering:
Why do you skip changing chipram mode if you find 68040.library? I have both loaded in my system.
Why do you assume chipram starts at $00004000? My custom Kickfile has it set at $0000F000. IIRC the default is $00001000?
You're doing a check on the chipmem mappings (don't have the bits in front of me now), but if it "fails" you loop through the loop once anyway?
You do exactly the same looping in the rom space handling which would explain why I see a change of only one page.


Are you sure 1.2 is the same version you are using?
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Old 20 October 2018, 16:48   #49
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Quote:
Originally Posted by NorthWay View Post
So I fired up Resource to take a look, and I sit here wondering:
Why do you skip changing chipram mode if you find 68040.library? I have both loaded in my system.
Why do you assume chipram starts at $00004000? My custom Kickfile has it set at $0000F000. IIRC the default is $00001000?
You're doing a check on the chipmem mappings (don't have the bits in front of me now), but if it "fails" you loop through the loop once anyway?
You do exactly the same looping in the rom space handling which would explain why I see a change of only one page.


Are you sure 1.2 is the same version you are using?
The 68040 has neither a "Store Buffer" nor a "Precise" mode for non-cache operation. The 68040 does have a "Serialized" mode for non-cache operation. Although some software apps may be less stable with the non-serialized mode FastCache040+ is not one of them. Hence, the default setting of the 68040.library for Chip RAM (either serialized or non-serialized) is unchanged.

Chip RAM starts @ $4000 on all official Kickstarts since OS 2.04. The space @ $1000 is already set to "Precise" even thought it's not part of Chip RAM (see above). FixMapP5 was never intended to support custom Kickfiles. So you might consider using SetCacheMode as an alternative.
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Old 20 October 2018, 22:38   #50
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Quote:
Originally Posted by SpeedGeek View Post
Hence, the default setting of the 68040.library for Chip RAM (either serialized or non-serialized) is unchanged.
Maybe I wasn't clear enough: You _will_ find 68040.library on my CS060 MK1 if you call FindName("68040.library"). That test tells you nothing that a check of AFB_68040 wont already give. The check for modifying chipmem settings is if you find 68060.library or AFB_68060.

Quote:
Originally Posted by SpeedGeek View Post
Chip RAM starts @ $4000 on all official Kickstarts since OS 2.04.
No. AFAIK the only Kickstart version that starts at $00004000 is 3.1.4.
My A4000D with 3.1 ROMs starts at $00001000. I just turned it on to be absolutely sure. Users with Macintosh emulators will have reserved the first $4000 IIRC.
And if you have a 68000/010/020/030 I think chipmem starts at $00000400.
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Old 21 October 2018, 19:10   #51
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** 11TH NEWS UPDATE **

FixMapP5 1.3 released

v1.3 - Swapped order of 68040/060 library test. Some OS 3.1
systems use a dummy 68040.library (which does not expunge)
and prevented the chip RAM change to precise. Thanks to
Northway for reporting this bug.

Quote:
Originally Posted by NorthWay View Post
Maybe I wasn't clear enough: You _will_ find 68040.library on my CS060 MK1 if you call FindName("68040.library"). That test tells you nothing that a check of AFB_68040 wont already give. The check for modifying chipmem settings is if you find 68060.library or AFB_68060.
OK, I understand now. Thanks.
FixMapP5 1.3 should solve the problem now.

Quote:
Originally Posted by NorthWay View Post
No. AFAIK the only Kickstart version that starts at $00004000 is 3.1.4.
My A4000D with 3.1 ROMs starts at $00001000. I just turned it on to be absolutely sure. Users with Macintosh emulators will have reserved the first $4000 IIRC.
And if you have a 68000/010/020/030 I think chipmem starts at $00000400.
EDIT:
I swapped Kickstart 2.04 (v37) and 3.1 (v40) ROMs and Chip RAM starts @ $400 but for Kickstart 3.9 (v45) it's @ $4000.

I guess my memory was not good enough to remember the extra "0" from the last ShowConfig results from 1-2 years ago.

So, I will now try to make a version to fix that problem as well.

Last edited by SpeedGeek; 22 October 2018 at 20:17.
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Old 23 October 2018, 16:05   #52
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** 12TH NEWS UPDATE **

FixMapP5 1.4 released

v1.4 - Added code to determine the Chip RAM start address from the
system memory list. Hopefully, this solves the problem with
Kickstart versions which config the Chip RAM differently.
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Old 25 November 2018, 18:43   #53
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** 13TH NEWS UPDATE **

FastCache040+ 2.0 released.

2.0 - Added code to enable only one DTTR when the Nest count
is one. Most systems have only one DMA driver and only need to
have 16MB of address space managed for this case.
Removed 1.9BR version which was over-rated due to most DMA
drivers operating at higher priority than typical user tasks.
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