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Old 09 May 2017, 19:38   #21
Akira
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You are right, what a moron I am . So you need the CPU at least.
Thanks for pointing it out.
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Old 08 June 2017, 02:17   #22
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Quote:
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Wicher 500i has been adapted to be mounted inside the enclosure Amiga 500.

Performance MC68000, cpu clock 50MHz (SysInfo 4.0, AIBB 6.5).
Mips: 4.40
Dhrystones: 4222
IDE transfer: ~3.1MB/s
RAM transfer: ~6.94MB/s

Upgade benchmarks:
Custom Kickstart 3.1, MC68HC000FN16@50MHz, scsi.device V46.0 and IdeFix97
IDE transfer speeds: ~5.8MB/s


is very, very speed

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Old 08 June 2017, 15:52   #23
Lord Aga
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very speed
Much wow

Keep up the good work!
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Old 18 September 2017, 01:31   #24
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I see these are back in stock -- has anyone tried one inside a 1000?
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Old 25 September 2017, 02:39   #25
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New version of software for Wicher 500i is available.

Download
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Old 25 September 2017, 03:14   #26
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spidi, would it be possible to integrate AR3 in Wicher 500i like in ACA500+? That would be amazing.
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Old 02 November 2017, 22:27   #27
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spidi, would it be possible to integrate AR3 in Wicher 500i like in ACA500+? That would be amazing.
The turbo card design would require minor modifications.
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Old 02 November 2017, 22:35   #28
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New version of the WicherInstaller v1.2 software is available.
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Old 28 December 2017, 03:13   #29
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New update for accelerator boards Wicher 500i and Wicher 500i Ex - WicherInstaller v1.4 and adding support for the MP3 hardware decoder - VS1003/1053 MP3 CODEC.




My installation of MP3 decoder

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Old 08 January 2018, 17:39   #30
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I picked up a Wicher 500i Ex card recently and put together a review for my YT channel

check it out if you're interested!

[ Show youtube player ]
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Old 11 January 2018, 13:44   #31
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Quote:
Originally Posted by spidi View Post
Wicher 500i has been adapted to be mounted inside the enclosure Amiga 500.

Performance MC68000, cpu clock 50MHz (SysInfo 4.0, AIBB 6.5).
Mips: 4.43
Dhrystones: 4247
IDE transfer: ~3.1MB/s (using IdeFix97 ~5.8MB/s)
RAM transfer: ~6.99MB/s
How many wait states against the memory at 50MHz? I guess it will be 0 wait states below some frequency?

Does it have a MapROM function so it can execute the important OS code in the kickstart at the full speed potential of the card?
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Old 12 January 2018, 16:26   #32
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@spidi are you going to document how to access the SPI interface? Would love to play with it.
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Old 12 January 2018, 22:34   #33
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@spidi are you going to document how to access the SPI interface? Would love to play with it.
Yes, SDK will be published soon.
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Old 12 January 2018, 22:57   #34
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How many wait states against the memory at 50MHz? I guess it will be 0 wait states below some frequency?
1 ws for 50MHz or one more extra. Up to 33MHz is 0 ws.

Quote:
Originally Posted by patrik View Post
Does it have a MapROM function so it can execute the important OS code in the kickstart at the full speed potential of the card?
Currently the card has no MapROM function.
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Old 14 January 2018, 00:50   #35
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1 ws for 50MHz or one more extra. Up to 33MHz is 0 ws.

Currently the card has no MapROM function.
Thanks for the info! Would it be possible to implement a MapROM function? With such a fast processor, without caches, it should improve OS performance quite a bit.
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