68k details

[meynaf]

Originally Posted by plasmab

I can put both chips on 10ns static RAM. The 6502 theorically maxes the RAM at 200MHz. The 68000 would need to go to 400Mhz... the first ARM maxes out at 100Mhz... same for the 040.

And then ? It is just that 6502 uses 1 clock out of 2 (and it does that by design !), 68000 uses 1 out of 4 (probably same), and ARM saturates the bus without any regard to dma or whatever.

Originally Posted by plasmab

Rubbish! A 68000 needs 4x 140ns per ram access. The first access on SDRAM/DDRx is 70-80ns and it’s 10-30ns to pull each sequential memory location thereafter depending on the memory type.

Not rubbish ! In comparison to the clock rate of a multi-ghz cpu, even 10-30ns is HUGE.

Originally Posted by plasmab

You don’t know what you are talking about.

People writing that kind of sentences usually are wrong.

Originally Posted by plasmab

I’ve built controllers for SDRAM and DDR.

Then you should know that in comparison to the cpu frequency (of cpus we have today), they have big latencies.

Originally Posted by plasmab

Plus a modem CPU pulls 128 bytes per access.

And has to wait 300-400 clocks for the first data to be available.

[plasmab]

Urgh. Ok. You will hear nothing against you beloved 68000. There is no point in discussion.

But if it was so good why is dead? It sucked. ARM has better latency and the x86 scaled better. Both are successful.

[meynaf]

Originally Posted by plasmab

Urgh. Ok. You will hear nothing against you beloved 68000. There is no point in discussion.

This is nonsense. I've written a big list of shortcomings in this same thread and I perfectly know the 68000's implementation isn't ideal.

But you have to admit that at 3Ghz a small 10ns is already 30 clocks, i.e. a lot.

Originally Posted by plasmab

But if it was so good why is dead? It sucked. ARM has better latency and the x86 scaled better. Both are successful.

ARM is used only because it's easy to licence, and x86's success only came because it was used in ibm pc. Without that, they'd be goners like 68k.

[plasmab]

Originally Posted by meynaf

This is nonsense. I've written a big list of shortcomings in this same thread and I perfectly know the 68000's implementation isn't ideal.

But you have to admit that at 3Ghz a small 10ns is already 30 clocks, i.e. a lot.

My point is .. and remains that the modern CPUs are limited by the RAM performance and the 68000 was limited by its own crappy bus interface. The number of. Cycles waiting is irrelevant. It’s the overall time elapsed that’s important.

[meynaf]

Originally Posted by plasmab

My point is .. and remains that the modern CPUs are limited by the RAM performance and the 68000 was limited by its own crappy bus interface. The number of. Cycles waiting is irrelevant. It’s the overall time elapsed that’s important.

And ? Let's admit the 68000 has a crappy bus interface. This can be fixed with a new implementation and does not make the cpu less good to code on.

[plasmab]

Originally Posted by meynaf

And ? Let's admit the 68000 has a crappy bus interface. This can be fixed with a new implementation and does not make the cpu less good to code on.

That’s all I was saying. Right from the start.

[meynaf]

Originally Posted by plasmab

That’s all I was saying. Right from the start.

It seems you were also saying that the 68000 has poor performance.
But in spite of its bad memory interface, it still ran circles around the cpus of its time. It took up to the 68040 before Intel, having better financial means, could finally catch up.

[plasmab]

Originally Posted by meynaf

It seems you were also saying that the 68000 has poor performance.
But in spite of its bad memory interface, it still ran circles around the cpus of its time. It took up to the 68040 before Intel, having better financial means, could finally catch up.

It could have had so much better performance if it’s bus interface didn’t suck. And that’s my issue with it. Other CPUs got closer to their theoretical max performance because the bus interface was less silly. Yes the 8086 was almost as bad.

So that’s why I say the memory performance is terrible on a plain 68000. The RAM could do about 70-80ns but the CPU took 4 x 140ns to do an access. That’s a lot of waste.

[meynaf]

Originally Posted by plasmab

So that’s why I say the memory performance is terrible on a plain 68000. The RAM could do about 70-80ns but the CPU took 4 x 140ns to do an access. That’s a lot of waste.

It sure is, but is that poor performance due to the memory interface, or to the mere fact it needs min 4 clocks for a single instruction ? This is a bigger performance killer anyway, as the 68k has enough registers to not spend all its time on memory.

68000 is a complex cpu that had to be implemented with very limited technology. It is not abnormal they had to do compromises.

[plasmab]

Or to put it another way. Modern CPUs have to wait on the RAM being ready. The 68000 could barely make the ram work at 15% of what it was capable of (unless you were doing read modify write instructions all the time). Other CPUs managed to use more of their available RAM bandwidth.

[plasmab]

Originally Posted by meynaf

It sure is, but is that poor performance due to the memory interface, or to the mere fact it needs min 4 clocks for a single instruction ? This is a bigger performance killer anyway, as the 68k has enough registers to not spend all its time on memory.

68000 is a complex cpu that had to be implemented with very limited technology. It is not abnormal they had to do compromises.

Yes. this is exactly the reason and it’s a poor design of bus interface IMHO. when it’s executing instructions the bus is idle when it could have been preemptively reading something.

Sure it was built with old tech but by the time the Amiga was launched it was a pretty ancient CPU. 5-6 years old?

[meynaf]

Originally Posted by plasmab

Or to put it another way. Modern CPUs have to wait on the RAM being ready. The 68000 could barely make the ram work at 15% of what it was capable of (unless you were doing read modify write instructions all the time). Other CPUs managed to use more of their available RAM bandwidth.

But could all that extra bandwidth really be used in actual machines ?

Originally Posted by plasmab

Yes. this is exactly the reason and it’s a poor design of bus interface IMHO. when it’s executing instructions the bus is idle when it could have been preemptively reading something.

Reading what ? It has no cache !

Originally Posted by plasmab

Sure it was built with old tech but by the time the Amiga was launched it was a pretty ancient CPU. 5-6 years old?

Yet chipmem bus on the amiga is rather something like 280ns.
Then 1 clock out of 2 is reserved for dma activity.
What remains then ? Just 1 mem cycle out of 4x140ns...

[plasmab]

Originally Posted by meynaf

But could all that extra bandwidth really be used in actual machines ?



Reading what ? It has no cache !



Yet chipmem bus on the amiga is rather something like 280ns.
Then 1 clock out of 2 is reserved for dma activity.
What remains then ? Just 1 mem cycle out of 4x140ns...

The lack of a prefetch cache is part of my point.

The RAM chips themselves are 70ns ... I’ve replaced enough of them to know. The 280ns is with a refresh cycle which doesn’t happen all the time.. but ok. You’re still only using 50%.

You are giving the reasons why it didn’t happen. I’m not saying the people who did it were stupid for not doing this I’m just showing that the bus interface could have given us so much more with a different design... and keeping the same instruction set.

[meynaf]

Originally Posted by plasmab

The lack of a prefetch cache is part of my point.

The RAM chips themselves are 70ns ... I’ve replaced enough of them to know. The 280ns is with a refresh cycle which doesn’t happen all the time.. but ok. You’re still only using 50%.

You are giving the reasons why it didn’t happen. I’m not saying the people who did it were stupid for not doing this I’m just showing that the bus interface could have given us so much more with a different design... and keeping the same instruction set.

Different design, same instruction set ? But we have this already. Perhaps 68020-30, 68040, 68060 fare somewhat better than old 68000 ?

[plasmab]

Originally Posted by meynaf

Different design, same instruction set ? But we have this already. Perhaps 68020-30, 68040, 68060 fare somewhat better than old 68000 ?

I already said this!

[roondar]

Originally Posted by plasmab

Yes. I give you it’s an apples and oranges performance comparison. Point remains... a plain 68000 takes 4 cycles to access the bus and the 6502 takes 2 base cycles. Plus the BBC makes its ram work on both edges of the clock.

My point is that it's wrong to only look at cycles needed. You seem to ignore that the 68000 was clocked much higher than the 6502 from the day 1 and that this difference in clock speeds only grew in later years (you can get a 4Mhz 6502 these days and a 42Mhz 68000). Yes, the 68000 needs 4 cycles to access memory. But it still has faster actual RAM access speeds (in nanoseconds) than the 6502 you're comparing it too. That this is a function of the clock speeds the CPU's ran at in practice doesn't matter for the end result.

Case in point: a 2Mhz 6502 takes two cycles to fetch 8 bits, a 7Mhz 68000 takes 4 to fetch 16 bits. Which of the two is actually accessing memory faster?

Right, the 68000 is. Which is exactly what my example showed: the 7Mhz 68000 absolutely trounces the memory copy speed of the 2Mhz 6502 manages.

Sure the 6502 only accesses 8 bits at a time and yes the 68000 is a better CPU. But it’s ram performance is awful.

The 'awful' ram performance of the 68000 (2 bytes per 4 cycles) fetches the exact same number of bytes per cycle as the 6502 (1 byte per 2 cycles) which has 'great' ram performance.

Which neatly ties to this:

I can put both chips on 10ns static RAM. The 6502 theorically maxes the RAM at 200MHz. The 68000 would need to go to 400Mhz...

True, but in this scenario the 68000 would give you 200 million bytes per second of memory bandwidth (4 cycles per 2 bytes), while the 6502 only gives you 100 million bytes per second (2 cycles per 1 byte).

Real world performance is much more important than theoretical stuff like 'does it saturate the bus'. You could just as easily argue that the 68000 way is actually beneficial as it allows for easy implementation of DMA subsystems that can boost the performance of the whole system.

Wait, there was a computer system in the mid 80's that did exactly that. I wonder what it was called :P

[plasmab]

Originally Posted by roondar

My point is that it's wrong to only look at cycles needed. You seem to ignore that the 68000 was clocked much higher than the 6502 from the day 1 and that this difference in clock speeds only grew in later years (you can get a 4Mhz 6502 these days and a 42Mhz 68000). Yes, the 68000 needs 4 cycles to access memory. But it still has faster actual RAM access speeds (in nanoseconds) than the 6502 you're comparing it too. That this is a function of the clock speeds the CPU's ran at in practice doesn't matter for the end result.

Case in point: a 2Mhz 6502 takes two cycles to fetch 8 bits, a 7Mhz 68000 takes 4 to fetch 16 bits. Which of the two is actually accessing memory faster?

Right, the 68000 is. Which is exactly what my example showed: the 7Mhz 68000 absolutely trounces the memory copy speed of the 2Mhz 6502 manages.

The 'awful' ram performance of the 68000 (2 bytes per 4 cycles) fetches the exact same number of bytes per cycle as the 6502 (1 byte per 2 cycles) which has 'great' ram performance.

Which neatly ties to this:
True, but in this scenario the 68000 would give you 200 million bytes per second of memory bandwidth (4 cycles per 2 bytes), while the 6502 only gives you 100 million bytes per second (2 cycles per 1 byte).

Real world performance is much more important than theoretical stuff like 'does it saturate the bus'. You could just as easily argue that the 68000 way is actually beneficial as it allows for easy implementation of DMA subsystems that can boost the performance of the whole system.

Wait, there was a computer system in the mid 80's that did exactly that. I wonder what it was called :P

The Atari STE... indeed

The Amiga 1000/500 didn’t do it properly. The ST uses the bus mastering system properly. The Amiga doesn’t. It just buffers the 68000 data bus from ram and makes the 68K wait...

You make all these defensive arguments about the bus performance. I disagree because it could have been better and did get better later. Why is it still relevant? Because the plain 68000 and SE versions are the only ones (as far as I know) still being manufactured.

[ross]

Originally Posted by meynaf

Because at least CLR on 68000 behaves as expected and the bug did not show on many machines (only on some Amiga's hardware registers), for many it was just a minor timing issue.

[OT]
Just out of curiosity. Is there any actual problem that CLR really can generate?

Taking into consideration only the standard hardware registers (chipset and CIA) the only ones that come to mind that can have side effects are the chipset's STROBEs and CIA's ICRs.
But in any case nothing that can generate serious problems (as long as it's not code out of control..).

[roondar]

Originally Posted by plasmab

The Atari STE... indeed

The Amiga 1000/500 didn’t do it properly. The ST uses the bus mastering system properly. The Amiga doesn’t. It just buffers the 68000 data bus from ram and makes the 68K wait...

Whatever, both interleaved memory for 68K and DMA. Which resulted in increased performance for both compared to not doing so. Just like the BBC Micro used rising and falling edges to increase performance compared to not doing so. Both ideas being a neat way to increase performance without increasing clock speed.

You make all these defensive arguments about the bus performance. I disagree because it could have been better and did get better later. Why is it still relevant? Because the plain 68000 and SE versions are the only ones (as far as I know) still being manufactured.

I am making 'defensive' arguments because you said:

Not the 6502 it doesn’t.

BBC B gets 0.5 mips at 2mhz. Same as the Amiga at 8mhz

Which is basically nonsense (in the sense that it suggests equality where none exists).

And when I pointed this out, complete with examples, you hinted/suggested the real world performance difference was more or less invalid because

Point remains... a plain 68000 takes 4 cycles to access the bus and the 6502 takes 2 base cycles. Plus the BBC makes its ram work on both edges of the clock

Which hugely misrepresents the real world performance difference between the two. Again.

The same goes for your static RAM example. That example is even worse because it's suggesting the 6502 is faster at accessing memory when in fact it is not doing any better than the 68000. Both of these CPU's would transfer the exact same number of bytes per second had they been clocked at the same speed. But the way you present it makes it seem as though the 6502 transfers twice the number of bytes.

To me that feels a little too much like misinformation (whether purposeful or not) and so I 'defend' against it by pointing out what the real world consequences/conclusions of your examples actually are. So people can see what you're saying is only true from a certain, rather theoretical, point of view.

And certainly not the 'what processor is actually faster/gives me better performance in the real world' point of view.

I'd do exactly the same in case someone where to start arguing that the Pentium 4 was a superfast processor because it could be clocked so high and thus could do so many instructions per second and access it's cache at these high clock speeds, while ignoring that the real world performance of it's competitors product (the AMD Athlon) was better even though it ran at a much, much lower clock speed.

[ross]

Originally Posted by roondar

The same goes for your static RAM example. That example is even worse because it's suggesting the 6502 is faster at accessing memory when in fact it is not doing any better than the 68000. Both of these CPU's would transfer the exact same number of bytes per second had they been clocked at the same speed. But the way you present it makes it seem as though the 6502 transfers twice the number of bytes.

Just to get along
You're both right, simply the 6502 if it had a 16-bit bus would access the memory at twice the speed of 68k.
But since we are in the real world, the 6502 actually reads the same data at (if it ever existed) same speed.