24 February 2018, 09:12 | #81 |
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27 February 2018, 00:53 | #82 |
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For those who are interested in the project for the a1200, here's a quick preview of the board that kipper has been working on lately.
All the code and board files will be opened up as soon as we have tested thoroughly, no point people playing catch up with us. |
27 February 2018, 09:33 | #83 |
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Very nice
Kipper2ks first version is running fine here. |
27 February 2018, 13:41 | #84 |
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Whatever happened to the PCI form factor?
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27 February 2018, 14:34 | #85 |
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K1208 & pci
The board will be sold in both variants,
the 1200 connector as well and the PCI edge converted version with adapter. The PCI version is nice for anyone who wants to take this further, it allows you to go prototyping at a very low cost. |
27 February 2018, 19:51 | #86 |
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How many layers is the PCB? Seems to be 4 from the look of the non-tracked via's.
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27 February 2018, 20:05 | #87 |
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Where are the sources? If they’re being sold you need to open them up
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27 February 2018, 20:08 | #88 | |
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Quote:
this board is not being sold, the only one that is opened up is the one that you already have sources for, (the basic 8mb board with the ide not working). As solidcore already stated when displaying the renderings we will open it up once we have sorted it out before blanks/kits/etc are offered for sale (The board is indeed a 4 layer board with a bigger cpld than previous) |
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27 February 2018, 20:09 | #89 |
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No problems. Thought it was already on sale from the responses.
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27 February 2018, 20:14 | #90 |
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27 February 2018, 21:08 | #91 |
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Yeah Ive only donated initially to kipper for parts and postage fees . It will be open source on GitHub but far from complete so nothing to release yet. New board has a bigger cpld and spi being designed from ground up. With possible features such as sd boot as well. China board house delays and everyone involved can only put a percentage of their time on this. Look forward to the new revision.
Edit: Today we decided to start a new clean VHDL project moving away from Verilog. Kipper and myself have began working with another individual who has a high level of cpld and fpga experience, we'd also like to thank matze for his experience and input into this project as far. Regardless, the project will remain open source, a github will open in the coming weeks. A 060 board is on the agenda as well, which we're excited about. Hmmm playing with cpld's is a lot of fun so we're going to experiment : sd / spi flash memory rom bootloading , akiko, and some other playful things. Updates will be posted as usual. Last edited by solidcore; 28 February 2018 at 02:06. |
28 February 2018, 11:10 | #92 | |
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Quote:
My idea is to use the "DiagArea" as part of an attached to an I/O device (virtual in your CPLD) linked in by the expansion.library. With this, you can have a small -4, -8 or -16 bit ROM which bootstraps (with existing KS ROM) reading from the SD card an "Image.bin" to FastRam (preserved during reset) and then resets the Amiga again to boot the KS from FastRAM. I actually think this is how the Blizzard Turbo Cards actually do it (can someone confirm this???). Sooooooo many ideas! Do you think working on Amiga hardware can be a full time job? |
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28 February 2018, 14:25 | #93 | |
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Quote:
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20 March 2018, 18:49 | #94 | |
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Quote:
or CF Adapters. Now with enough memory, I don´t care about the CF adapter, because LAN would give me even nicer copy-possibilities than CF Still, the CF card makes it easier than configuring Amiga LAN...but I´ll figure that out... |
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01 April 2018, 15:38 | #95 |
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Completely new: VHDL firmware, SPI and SD.Device We're now moving onto 'other features' Last edited by solidcore; 01 April 2018 at 15:44. |
01 April 2018, 16:52 | #96 |
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02 April 2018, 20:44 | #97 |
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Awesome news :-)
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26 April 2018, 06:07 | #98 |
I miss my A1200
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Any updates on this one? It's been super exciting to read about do far.
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26 April 2018, 08:19 | #99 |
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The solidcore post was dated 1/4 ... April fool?
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26 April 2018, 10:52 | #100 |
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Not at all. It's very real, see images below. We've all been busy so not much news I'm afraid.
Regarding the release of the driver, it will be published soon, I'll update the thread when that happens. However, the driver is unfinished and still requires a non-blocking message queue, support for SCSI, and hot-swap disk change. Performance is around 187,000 BYTES/Second (based on sysinfo speed test) and this is with a SPI clock of 14mhz (amiga clock OR pal clock/2). The type of card SD, SDHC, SDXC doesn't change the performance speed at 14mhz/512 Block Size, however, options for block sizes are 1 through to 16384 but I've not had time to test this and it was agreed for the time being for compatibility reasons that we leave it set at 512. Finally, I believe it'd be nice if we got an alternative to fat95 which doesn't try to walk the fat on FAT32, as it has considerable mount delay as opposed to FAT formatted SD cards. *Teaser* We're now sniffing ETH packets but yet to tie it into a stack to really have a play. soon Last edited by solidcore; 26 April 2018 at 11:43. |
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