AGA integration in Apollo core : work in progress

[Gorf]

Originally Posted by TrashyMG

That said, I've never encountered any hard crashes or reboots with WHDload on any of the games I've played on my Vampired A600. Of course haven't tried any AGA games yet, waiting for the Gold 3 core for that.

Sure - most games don't crash randomly. This was the hard lesson programmers had to learn back than: if you do something stupid everything goes down.

[grond]

OK, since a DMA controller is so much better than a 2nd CPU, I bet you are glad to hear that the DMA controllers in the Apollo Core are not going to disappear with the introduction of hyperthreading. Why make it look like it was an either-or question?

[Gorf]

Originally Posted by grond

OK, since a DMA controller is so much better than a 2nd CPU, I bet you are glad to hear that the DMA controllers in the Apollo Core are not going to disappear with the introduction of hyperthreading. Why make it look like it was an either-or question?

Wasn't it you, who claimed it is a wonderful idea to use the CPU as DMA-controller?

[grond]

Originally Posted by Gorf

Wasn't it you, who claimed it is a wonderful idea to use the CPU as DMA-controller?

In a single-threaded OS, yes, I still think it is a good use of a 2nd CPU.

[Gorf]

Originally Posted by grond

In a single-threaded OS, yes, I still think it is a good use of a 2nd CPU.

but not instead of a real DMA-controller.

As I said earlier: I still think the hyper-mode is a good idea. And I hope it will put to better use.

[grond]

Originally Posted by Gorf

but not instead of a real DMA-controller.

I still haven't understood why. The DMA controller and the CPU are both able to saturate the memory bus but the CPU can do more than simple copying. How resources (most of all mem access) are distributed among the main CPU and the DMA or the secondary CPU is a matter of the implementation and does not depend on the unit to which the mem interface is assigned to being a DMA controller or a CPU. If the DMA controller or DMA HT is allowed to be "nasty", it could starve the main CPU. In the end there is a fixed memory bandwidth that needs to be distributed between the CPU AOS runs on and the 2nd unit, whether it be a DMA controller or a CPU.

[Gorf]

Originally Posted by grond

I still haven't understood why.

pandy71 explained it very well. Read his post again.

Take into consideration that the CPU has caches, that are rendered useless for big memory operations.

[pandy71]

Originally Posted by grond

I still haven't understood why. The DMA controller and the CPU are both able to saturate the memory bus but the CPU can do more than simple copying. How resources (most of all mem access) are distributed among the main CPU and the DMA or the secondary CPU is a matter of the implementation and does not depend on the unit to which the mem interface is assigned to being a DMA controller or a CPU. If the DMA controller or DMA HT is allowed to be "nasty", it could starve the main CPU. In the end there is a fixed memory bandwidth that needs to be distributed between the CPU AOS runs on and the 2nd unit, whether it be a DMA controller or a CPU.

Well... look at RPi3 which is 4 core ARM when compared to single core RPi1 however memory subsystem architecture is almost same - so yes - 4 cores sharing bus with GPU and few other blocks (also DMA) will reach in unavoidable way bus saturation, partially this may be reduced/workarounded by aggressive CACHE design (large CACHE, complex architecture) but at some point you will reach bottleneck case - insufficient bus throughput will affect performance.
You can always use faster RAM, increase bus width, increase clocks, use tricks (interleaving etc) however all this costs and never provide 100% satisfactory solution.

[idrougge]

Originally Posted by meynaf

I wrote nothing about applications, i wrote about debugging.
Enforcer and similar tools are very useful for it. But you must be a coder to know that.

You can't be much of a coder if you require a debugger to write hyperthreaded applications.

[Gorf]

Originally Posted by idrougge

You can't be much of a coder if you require a debugger to write hyperthreaded applications.

I am sure your code is always bug-free and you never need a debugger.

[idrougge]

Only the best coders may code for the Apollo core, in pure 68080 assembly.

I mean, having a new architecture take developers into consideration is just silly. Developers are just a minority, although they do produce 100 % of all software. But who needs software when you can have hardware?

[meynaf]

Originally Posted by idrougge

You can't be much of a coder if you require a debugger to write hyperthreaded applications.

This isn't what i wrote.

Originally Posted by idrougge

Only the best coders may code for the Apollo core, in pure 68080 assembly.

Then there will be no coder for it

Originally Posted by idrougge

I mean, having a new architecture take developers into consideration is just silly.

No, it's not. This is how original 68000 was designed.

Originally Posted by idrougge

Developers are just a minority, although they do produce 100 % of all software.

Make software production easier and you'll get better quality software from them. Make software production tougher and you'll get bloatwares. As easy as that.

Originally Posted by idrougge

But who needs software when you can have hardware?

Everyone, because hardware is useless without software...

[grond]

Originally Posted by Gorf

Take into consideration that the CPU has caches, that are rendered useless for big memory operations.

What CPU? Are we really turning meynaf's statement "In fact hyperthreading is the most useless thing ever added to that core" into a vain discussion about who can cite the highest number of buzz words?

Originally Posted by pandy71

Well... look at RPi3 which is 4 core ARM

No, I won't look at the RPi3 with a 4-core ARM. I'm looking at the 080 and an Amiga running AOS or AROS.

[Predseda]

I want to run Workbench 3 in 640x512 in 256 cols reasonably quickly. That is what I expect from a Vampire.

[pandy71]

Originally Posted by grond

No, I won't look at the RPi3 with a 4-core ARM. I'm looking at the 080 and an Amiga running AOS or AROS.

So instead pushing for hyperthreading you should push for more cores... they are more efficient than HT.

[grond]

Originally Posted by pandy71

So instead pushing for hyperthreading you should push for more cores... they are more efficient than HT.

I'm not pushing for anything and pushing doesn't have any effect on this project, haven't you noticed?

Obviously a full second core is better than a HT virtual core but it's something like 15,000 LE for a second core vs. 400 LE for the HT one.

[Gorf]

Originally Posted by Predseda

I want to run Workbench 3 in 640x512 in 256 cols reasonably quickly. That is what I expect from a Vampire.

Hot coffee in the morning an a decent breakfast! That is the least I can expect, isn't it?

[Overflow]

Vampire 600 V2 GOLD3 bring-up / Kioea by Mad Wizards (AGA/FPU-Demo)


Tested on an Amiga 600 with Vampire 600 V2 GOLD3 Beta + SAGA/SoftFPU. Audio and video are played through HDMI.

[ Show youtube player ]

[emufan]

not so bad. so now we can expect some demonstration of someone using Lightwave 5 / tvpaint on the vampire

[Locutus]

Skip to 1:16, that looks painful