10 January 2020, 19:51 | #21 | |
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 49
Posts: 26,516
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Quote:
This is difficult to visualize.. Perhaps it needs some special dma debugger mode to see what really happens, in real time. |
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10 January 2020, 20:57 | #22 |
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Location: Norway
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That might explain why period 113 didn't work with len 2270.
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07 February 2020, 19:55 | #23 |
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 49
Posts: 26,516
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Few days ago I was doing unrelated interrupt line to IPL line change timing tests and noticed there is 2 CCK delay between first AUDxDAT Agnus DMA write and before Paula IPL line changes state.
I thought this might have something to do with this guirk. And it does, today I did some tests and if I add 2 cycle delay before AUDxLEN counting down is handled in emulation, "quirk range" matches real hardware exactly. TODO: find some optimal emulation that only does this when it is really needed, to not waste CPU time for something that almost never happens. |
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