Terrible Fire Accelerators

[8 Bit Dreams]

Originally Posted by plasmab

EDIT: If i got through the hell of putting level shifters on there its getting SDRAM at the same time.

Yeeeah!
That's what i wanted to hear!
But...let's put these plans on a shelf for a while, otherwise there will be a million comments asking for 128MB cards IMMEDIATELY (Amiga2000, where are You!?)
hope this RAM bug will be caught soon, then we can speak about backport for TF530 and maybe TF520..

Getting asked about TF534 from time to time, will it be released before Christmas/is this the last issue before release, or maybe You planning to do some Maprom/SPI related tasks before?

[plasmab]

Actually will release it when we sort this zorro ii issue. SPI is a nice to have.

[plasmab]

Does anyone know how one builds systest. I need to add some test bits to it.. seems to want some funny elf version of gcc. I have 3 68k gcc toolchains and they all error.

[SukkoPera]

I seem to recall I once built it with a crosstool-ng toolchain.

[supaduper]

N/a

[8 Bit Dreams]

Originally Posted by plasmab

Does anyone know how one builds systest. I need to add some test bits to it.. seems to want some funny elf version of gcc. I have 3 68k gcc toolchains and they all error.

Did You saw Keir's github already?
https://www.google.de/url?sa=t&rct=j...7hMxC2vQoicPGv

[plasmab]

Yes but there are no instructions on how to build. I need to make modifications to report more info.

Viktor, is you have CDIS jumper try closing it and testing a zorro ii ram card

[pgovotsos]

Originally Posted by alenppc

No change on the Microbotics side ram expansion, still shows up as defective. I wonder how other CPU accelerators deal with this.

Can the A500/1000 side expansions be considered proper Z2 boards or are they all assuming a 68000 CPU only?

I know that A2000 cards such as Commodore 2052/2091 and similar work with accelartors but maybe A500/1000 don't.

I don't know about all combinations but the Starboard worked with a MMR on a 1000. Wasn't a lot of point to it once I added the memory board to the MMR so removed it but it did work.

I don't remember exactly but I seem to remember that the Insider worked with one of the side accelerators on the 1000.

[8 Bit Dreams]

Originally Posted by plasmab

Viktor, is you have CDIS jumper try closing it and testing a zorro ii ram card

Sure!
CDIS jumped mounted, this time took Logica Diagnostic ROM, with a hope to see faulty address:


Don't know will it help You to go further, but this is what i get..seems there are different error addresses each time i run this test..

[plasmab]

Originally Posted by 8 Bit Dreams

Sure!
CDIS jumped mounted, this time took Logica Diagnostic ROM, with a hope to see faulty address:
Attachment 60376
Attachment 60377
Don't know will it help You to go further, but this is what i get..seems there are different error addresses each time i run this test..

thats useful. What diagnosics rom is that? i just need to capture the issue happening on the LA to figure out whats happening. :/

[8 Bit Dreams]

Oh, that's old Logica ROM from 1997, useful tool, need to admit..

[plasmab]

Originally Posted by 8 Bit Dreams

Oh, that's old Logica ROM from 1997, useful tool, need to admit..

I have a few suspicions about the issue. Just need to build the software to be able to reproduce it on the scope.

[plasmab]

Originally Posted by SukkoPera

I seem to recall I once built it with a crosstool-ng toolchain.

Couldn’t find it in easy apt-get-able form. Will need to build from source. :/

[SukkoPera]

Well, that's pretty easy actually, it is menu-driven. Give it a go!

[PR77]

Originally Posted by plasmab

Ok. INT2 cable no longer needed on the TF534... Epic Win.

EDIT: Expect stream later after celebratory steak.

Plasmab, which register did you manipulate to trick the INT2 is asserted? Additionally, is this register polled cyclically by the OS? If yes, wouldn't the INT2 assertion still be faster (I understand the reason for removing it- only a question).

I was thinking of the idea of using the IPL[2:0] <= 3'b010 when GAYLE INT is active (for my Rev4 PCB), however I have no means to determine if this is the same as INT2.

[plasmab]

Originally Posted by PR77

Plasmab, which register did you manipulate to trick the INT2 is asserted? Additionally, is this register polled cyclically by the OS? If yes, wouldn't the INT2 assertion still be faster (I understand the reason for removing it- only a question).



I was thinking of the idea of using the IPL[2:0]

INTREQR.. it’s literally 2 fast cpu clock cycles slower than INT2 per interrupt... which is sod all on context.

I also assert the IPL lines. You then need to cope with IACK.

Simply asserting IPL lines doesn’t work. Tried on the TF534 Rev 1. There is even a video of this somewhere.

[plasmab]

Basically unless you patch INTREQR it’s seen as a “spurious” interrupt and ignored.

I don’t get why you thought I was letting the OS poll? I got 4-5Mb/s on stream. You’re at tape speeds polling.

[SukkoPera]

Are you going to make the INT2 wire optional or remove it altogether?

I mean: would those who are still willing to install it benefit from (slightly) better performance? Or would they just not have that option anymore?

[Toni Wilen]

Small warning: this hack is probably safe in AmigaOS because exec interrupt handlers check both INTENAR and INTREQR but it can cause bad side-effects in other operating systems (or if program that takes over the system and uses IDE interrupts) which may only check INTREQR and execute the interrupt even when INTENA has matching interrupt bit disabled. Or crash if very unexpected IDE interrupt comes even when INTENA has all interrupts disabled.

[plasmab]

Originally Posted by Toni Wilen

Small warning: this hack is probably safe in AmigaOS because exec interrupt handlers check both INTENAR and INTREQR but it can cause bad side-effects in other operating systems (or if program that takes over the system and uses IDE interrupts) which may only check INTREQR and execute the interrupt even when INTENA has matching interrupt bit disabled. Or crash if very unexpected IDE interrupt comes even when INTENA has all interrupts disabled.

I’ll patch INTENA on the final version.

I dislike how Amiga OSes assumes interrupts are off by disabling INTENA though. You should mask them off in SR if you want to be safe. Spurious interrupts do occur.

I’m not giving the INT2 option simply because I didn’t put a pull up on it and I can’t make it work both ways within one firmware. And no I don’t want to support multiple firmwares. I take the Apple model of reducing my workload by taking away your options.

Mod it yourself and support it yourself.

I will try and make it as fast as a real INT2 though. The implementation I have is pretty slow and safe.