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Old 23 March 2013, 15:25   #1
majsta
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Vampire 500 project started

So Amiga 500 will get FPGA version soon.
Here are the features:
-- Some FPGA core
-- 64 megabytes of mem
-- Micro SD
-- wireless slot
-- spi slot ( for RTC or something you want)
-- PC/2

All slots will be compatible with cheap arduino based upgrade boards. Performance between 6 and 9 Mips I don't know yet.
What is done so far, nothing much but hardware design is almost done. Also I have got permission to use wireless codes build in C. Rest of softcore design should be the same like in Vampire 600 project I only need to include 3 more signals but that shouldn't be a problem. Regarding MicroSD goal is to have two partitions on for workbench and one for some kickstart so we will see...
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Old 23 March 2013, 20:43   #2
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sounds interesting!
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Old 23 March 2013, 21:19   #3
Lord Aga
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Woohoo go majsta
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Old 24 March 2013, 15:18   #4
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Approximate price? Please consider to implement some barrel shifter + perhaps simple RISC (copper like) coprocessor to process data. It will be very nice to have more RAM that can be used as RAD: like device.
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Old 24 March 2013, 16:58   #5
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I don't know about the price yet. I just ordered some components for 10 boards. I will not add additional features because I included most of the ports for adding whatever somebody wants if have enough knowledge. Like I said on my website I have privilege to see Amiga 500 for about 15 minutes in 1999 so I don't have it and have no idea what I can include. Few days I have ordered A500 motherboard and it should arrive shortly then when I get my hands on the board I will investigate more. For now I will try to create price as low as possible and if you don't like the price once finished design will be opensourced so...
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Old 25 March 2013, 18:21   #6
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Thx majsta, i see your point - i will wait for your project, good luck.
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Old 10 April 2013, 23:03   #7
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Here is final design of accelerator. It was much harder than designing something for A600 so those days PCB goes to production with this look.



Uploaded with ImageShack.us

Last edited by majsta; 11 April 2013 at 12:25.
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Old 10 April 2013, 23:32   #8
mfilos
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Nice work there Majsta mate!
Seems really cool
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Old 11 April 2013, 06:33   #9
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woww, i want to test this thing!!!
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Old 12 April 2013, 19:55   #10
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More reasons to raid the bank and wind my lass up lol!

I have just splashed out for more upgrades and would be straight on one of these when finished
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Old 09 July 2013, 22:50   #11
majsta
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Ok since few days A500 is started with Vampire500, so next logical step was to add IDE controller and that was simple task so code is written in 10 minutes. Then I realized that there is no autoboot option and that I need to solve 2 additional wires /OVR and /INT2.
For OVR it was easy task and internal DTACK was created but it seems that Gayle manual is just not enough for me to understand generation of INT2. So can someone in simple words explain to me those relations between DA8000, DA9000 and DAA000 and bit 15. And what IRQ request from IDE has to do with them, he needs to activate something.
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Old 10 July 2013, 06:25   #12
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looking good, lots of good things on the horizon
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Old 10 July 2013, 09:14   #13
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Originally Posted by majsta View Post
So can someone in simple words explain to me those relations between DA8000, DA9000 and DAA000 and bit 15. And what IRQ request from IDE has to do with them, he needs to activate something.
DA8000: current status of interrupt lines.
DA9000: currently active interrupts. ("INTREQ")
DAA000: enabled interrupts. ("INTENA")

You only need to care about highest bit (IDE interrupt). Other bits are PCMCIA only. You also need to implement gayle id register, wrong id = ide driver won't initialize.
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Old 10 July 2013, 14:10   #14
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Thank you but it seems that all of this is more complex than I was thinking. I just don't get it what do I need to do.
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Old 10 July 2013, 14:41   #15
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Thank you but it seems that all of this is more complex than I was thinking. I just don't get it what do I need to do.
DA9000 highest bit is set and INT2 is active when DAA000 highest bit is set and IDE interrupt line is active. Simple enough?

DA8000 can be ignored, at least when using standard ROM ide driver.
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Old 10 July 2013, 20:08   #16
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Hm it seems that something is wrong here regarding because I can't detect IDE space because it seems that gary blocks it before somehow so I can't perform anything since there is no proper detection of $DA0000 - $DA7FFF space. So somethings needs to be done before. more investigation needed here.
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Old 11 July 2013, 16:55   #17
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Is it possible that because gayle is not identified properly that CPU refuses to decode DAxxxx space. It makes sense because currently on that specific space TG68 is in 01 state(no memaccess). Maybe before all of this I need to create Gayle identification but then again all of this needs to be done before or when CPU is just started.

@Toni does this make any sense and how to identify Gayle, again please in simple words
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Old 11 July 2013, 17:06   #18
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There's no Gayle in A500.
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Old 11 July 2013, 18:11   #19
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@Toni does this make any sense and how to identify Gayle, again please in simple words
You should see 1 write and 8 read accesses to 0xDE1000.

KS detects Gayle type by accessing address DE1000 (byte wide)
Write anything: reset ID config.
Read: bit 7 becomes bit 0 of ID value
Read: bit 7 becomes bit 1 of ID value
and so on. until all 8 bits have been read.

0xD0 = Gayle. 0xD1 = AA Gayle. Any other value: No gayle.

Quote:
There's no Gayle in A500.
No but board includes "emulated" Gayle IDE.
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Old 12 July 2013, 01:23   #20
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Forgive me majsta but instead of finishing A600 project you started A500 accelerator, clearly not being even familiar with this Amiga. Can I ask why?
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