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Old 23 June 2017, 00:12   #1381
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In the meantime stay tuned this weekend.. I am prepped and ready to design a cd32 card live on stream... bit of an experiment but we'll see how we go.
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Old 23 June 2017, 01:45   #1382
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In the meantime stay tuned this weekend.. I am prepped and ready to design a cd32 card live on stream... bit of an experiment but we'll see how we go.


I'd like to check it out, but I'm on the other side of the world. If you can give a heads up on the time, I'll have a gander.
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Old 23 June 2017, 03:11   #1383
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I've considered it, but the initial release of the firmware doesn't seem to corrupt memory (yet introduces other complications.) I don't know of any others testing REV 3 just yet, either.
I am no wizard at this, just my observation..... For the record I could be talking shit, but it something to look at...

Steve used AS7C4096, in the data sheet, it states....

Quote:
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written
on the rising edge of WE (write cycle 1) or CE (write cycle 2).
So is that asserting high, or asserting low ?

Because on the chips you are having issue with, it states that a Write cycle CS and WS are asserted low. I would have thought an assertion of the RISING edge is a high ?

Then, on Steve's choice of chips

Quote:
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high.
But on your chips, Read cycles are established by asserting WE and CE to LOW....

Your choice of chips mate, assert signals in a different manner to what Steve used.

This is the way I read it and as I said, I could be full of shit so I am happy to be proven wrong.

They may be Pin for pin exact, same package, but the way the chip asserts read and write (High and low signals on CS, WE etc) is wrong, you are getting clashes.

At the VERY least you need a revision of the RAM CPLD to reflect the different assertion states in the Chip select and Write enable lines for your ram.
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Old 23 June 2017, 05:40   #1384
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The RAM is on the wrong side of the bus.. You want something that the 030 can access quickly.
No, no I don't. The TF5xx boards already have RAM in the 32bit FAST RAM space. This is to fill in the standard 8Mb FAST RAM space that many programs and games require to operate.

Since we already need a relocator board for most applications in order to close the case (certainly on the A500 and A1000), it seems a waste not to include the FAST RAM on the relocator.

Last edited by Tachyon; 23 June 2017 at 05:46.
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Old 23 June 2017, 06:45   #1385
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...
But on your chips, Read cycles are established by asserting WE and CE to LOW....
...
From http://www.mouser.com/ds/2/198/61-64C5128AL-258414.pdf Page 8:
"Notes: /WE is HIGH for a Read Cycle."

So I think his RAM chips are probably fine.
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Old 23 June 2017, 07:01   #1386
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From http://www.mouser.com/ds/2/198/61-64C5128AL-258414.pdf Page 8:
"Notes: /WE is HIGH for a Read Cycle."

So I think his RAM chips are probably fine.
WE High, but CE LOW. TF530 chips need WE and CE High.

Oh well it was a thought, along the lines of pin correct but there was a signal conflict with the way the chip expects pins to be asserted to enable modes.
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Old 23 June 2017, 07:46   #1387
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Nah - it's /CE Low for Read/Write on the AS7C4096A's as well:

http://pdf1.alldatasheet.com/datashe...AS7C4096A.html (truth table on page 2)
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Old 23 June 2017, 07:52   #1388
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No, no I don't. The TF5xx boards already have RAM in the 32bit FAST RAM space. This is to fill in the standard 8Mb FAST RAM space that many programs and games require to operate.
This intrigues me. Which games only support zorro 2 memory? I know of some that need C00000-memory.
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Old 24 June 2017, 21:00   #1389
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Would this be a relative easy add-on for the tf534? http://www.vesalia.de/e_a500clockport.htm
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Old 25 June 2017, 23:36   #1390
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Would this be a relative easy add-on for the tf534? http://www.vesalia.de/e_a500clockport.htm
Should be possible. You could probably make this happen on the TF530 by reprogramming the SPI pins and splitting the pins needed out from the IDE interface.
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Old 26 June 2017, 09:53   #1391
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After posting last week, about submitting boards to DirtyPCB's and sent to printing the next day (Monday cut off), I got a notification this morning (AU TIME), Boards are in the mail......

Just thought people might want to see the average turn around time.
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Old 26 June 2017, 10:09   #1392
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Would this be a relative easy add-on for the tf534? http://www.vesalia.de/e_a500clockport.htm
Could you do it, yes. The top two chips are 74HC series chips (Depends on the specific gates in the chip, I cant see the numbers after 74HC), the third on the bottom, I do not know.., it will not show up on zoom.

Buy one, trace the board, then once Steve releases the TF534, you could add it via Eagle. Yeah ! You have the 68000 socket already, add the 3 74HC series, and 2 headers and bobs your uncle. How you route it, thats your problem I have now learned enough through Steve's videos to add something like that on to the schematic page of Eagle..., haven't learned enough about routing yet though. (Hence my comment on his latest videos about adding a 68882 to a 68000 socket) .... Yes according to Motorola, 68882 will happily reside on a 16bit bus, you need a bit of Address decoding, and Chip Select.. but it is doable.

http://amiga.resource.cx/photos/phot...res=hi&lang=en

There you go, all 3 are 74HC series)
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Old 26 June 2017, 10:15   #1393
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Could you do it, yes. The top two chips are 74HC series chips (Depends on the specific gates in the chip, I cant see the numbers after 74HC), the third on the bottom, I do not know.., it will not show up on zoom.



Buy one, trace the board, then once Steve releases the TF534, you could add it via Eagle. Yeah ! You have the 68000 socket already, add the 3 74HC series, and 2 headers and bobs your uncle. How you route it, thats your problem I have now learned enough through Steve's videos to add something like that on to the schematic page of Eagle..., haven't learned enough about routing yet though. (Hence my comment on his latest videos about adding a 68882 to a 68000 socket) .... Yes according to Motorola, 68882 will happily reside on a 16bit bus, you need a bit of Address decoding, and Chip Select.. but it is doable.



http://amiga.resource.cx/photos/phot...res=hi&lang=en



There you go, all 3 are 74HC series)


You don't need the chips. The CPLDs can do the same job


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Old 26 June 2017, 11:04   #1394
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You don't need the chips. The CPLDs can do the same job

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Well what I was saying Yesterday on the stream, I figured out Eagle to do the Schematic bus, nets and stuff..

But CPLD and Routing, You are the god. How many VIA's again on the CD32 ram board ??

Here is a CDTV clockport design.

http://www.ianstedman.co.uk/Amiga/de...clockport.html

Last edited by whiteb; 26 June 2017 at 11:28.
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Old 26 June 2017, 11:09   #1395
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I added via stitching between the ground planes so about 180 in the end


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Old 26 June 2017, 11:19   #1396
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Well what I was saying Yesterday on the stream, I figured out Eagle to do the Schematic bus, nets and stuff..



But CPLD and Routing, You are the god. How many VIA's again on the CD32 ram board ??

I was trying to demo how easy this all is not how God like I am. Hmmmm.




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Old 26 June 2017, 12:30   #1397
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Sorry if this sounds stupid, but you've designed a card but havent produced it. DO you know if it works? Tested?
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Old 26 June 2017, 12:33   #1398
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Sorry if this sounds stupid, but you've designed a card but havent produced it. DO you know if it works? Tested?

Of course not. It's being made as I type. We will find out soon.


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Old 26 June 2017, 12:37   #1399
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Ah ok thanks. Bit late to the party so wasnt sure how it works but now ive got the idea.

Good luck!
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Old 26 June 2017, 13:24   #1400
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Ah ok thanks. Bit late to the party so wasnt sure how it works but now ive got the idea.

Good luck!


It's based on the TF530 IDE and RAM designs so barring a mistake from me during design it should work. This stuff is really easy. No clock domains to cross even


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