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Old 10 May 2011, 03:36   #21
Zetr0
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this thread gives me a warm fuzzy feeling =)
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Old 10 May 2011, 03:40   #22
Kai
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It'll make me warmer and fuzzier once pandy fiddles with the schematic/layout and gets the Gerber out for all
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Old 10 May 2011, 05:07   #23
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Quote:
Originally Posted by pandy71 View Post
Kai THX! and no problem - can't promise anything but i will try to check component placing and maybe some traces routing.

OK, seems that my Eagle is not able to create board bigger than 80x100mm - to small even to place components... KiCAD is not able to import libraries and schematics from Eagle - today i give up...
Do you have the shareware version of Eagle, i know that will only allow boards up to a certain square inch size ?

I can investigate cost of 4 layer board, its a little more than a 2 layer but you probably eed it for noise abatement and just the actual complexity of the circuit, also, what is the minimum trace size ?
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Old 10 May 2011, 09:43   #24
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@kipper2k

I have freeware version of Eagle - this one have this type of limitations - maybe i will try to use older version (latest is 5.11) - i should have somewhere old 3 or 4 series eagle with less limitation - KiCAD is good alternative however lack of libraries comparable to Eagle -creating own library with verification for parts used in this accelerator board will took at least 2 weeks (mostly weekends). Anyway i will try to use older Eagle.
Also i will try to use 2 layer board - this should be doable with careful routing.

@discussion about parts
GAL can be erased and reused - so no problem at all with older parts unless they are not OTP. Modern CPLD can be used to add value (DRAM controller + timing, maybe other functions but i still have strange idea about FPGA on board and add even more functionality like for example multimedia coprocessor - reprogrammable one)

btw

SMT sometimes can be worse than normal parts (especially with 2 layer boards SMT is less router friendly)
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Old 10 May 2011, 11:08   #25
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with eagle free 2 layer move gal and pal under 68000 optmize pcb, i suppose
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Old 10 May 2011, 12:00   #26
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Yah - the reason i went with a 4-layer PCB is that everything got a lot easier to route, with dedicated power and ground layers. 2-layer is *very* hard to do, change the routing grid to 10mm at least, otherwise the autorouter will get to about 80% and then give up!

I use Eagle 5.7 Pro (the $1500 version!), so i can have as many layers as i want, and whatever board size i desire, so its really a matter of the schematic being fettled with.

I don't mind spending a day routing it - as long as someone gives me the dimensions of the board, to ensure it doesn't foul any internal parts.

If someone adds the decoupling capacitors to my schematic, and the power supplies for the glue logic, i'll do the rest, and knock out a gerber
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Old 10 May 2011, 13:15   #27
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On 2 layer board - autorouter simply not work - only manual routing.
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Old 10 May 2011, 13:40   #28
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Concentrate on the schematic - i'll upload the latest version in a minute - i changed some of the discrete resistors to resistor networks (SIL).

** EDIT **

Pandy - use the same schematic link i gave you - its been updated!

Last edited by Kai; 10 May 2011 at 13:57.
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Old 10 May 2011, 14:42   #29
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...does this look better?


Last edited by Kai; 16 February 2014 at 00:46.
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Old 10 May 2011, 23:30   #30
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Hi,

Before I continue, I just want to say that I am trying to provide practical advice based on a number of years of experience.

The captured design, will not work as it stands but it can do with some effort.

This design needs decoupling capacitors, the original schematics list 33 capacitors ranging from 100nF to 47uF. As a minimum they must be added to the design. I would also add some 10nF capacitors around the logic and the CPU for higher frequency decoupling.

Have you checked that the TI PAL parts can be successfully programmed with JEDEC files from another Vendor?
If they can not, can you find a device fitter that supports these TI parts so you can re-compile.

Also do we know what speed grade the original PALS were? Can't see the full part numbers here: http://amiga.resource.cx/photos/phot...res=hi&lang=en

In 2011 we should not be designing PAL/GALs unless there is a very good reason, newer, smaller, lower power parts are available.

I would use something like this:
http://uk.farnell.com/xilinx/xc9572-...-5v/dp/1193231
In circuit programmable and PTH PLCC sockets are available.

Reading the documents, there appear to be noise issues. I can see how this could happen.

Going to a 4 layer PCB will help a lot. The power planes and the option of controlled impedances will help but there is more you can do.

There are two types of engineer, those who have signal integrity problems and those who know they WILL have signal integrity problems. The mid 80s PAL/GAL devices were notorious for noise problems, if not handled properly. Rise fall times of 1-4ns can wreak havoc if not dealt with.

The fixes are not too difficult.

Attached is an example of an un-terminated clock signal, not too pretty.

As a baseline, provision for a series resistor, on all signal lines that go off card. So this includes the data-bus and control strobes back to the 68000 socket. Some critical signals, to be defined, may require provision for a small (few pF) capacitor, which with the resistor, forms a low pass filter to remove noise.



If you require any further advice, I am here to help.
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Old 11 May 2011, 00:01   #31
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is possible use one chip as pal+gal+74xx?
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Old 11 May 2011, 00:27   #32
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I know that the caps needed to be added, but the way they were laid out on the original schematic, made no sense, hence my omitting them from the schematic for the time being...

The PAL code already exists in its raw form, in the PDF i linked you to. It doesn't matter about the manufacturer, they all work in the same way, so you can burn the .jed, or compile from scratch if you prefer.

PAL's and GAL's exist in the original design (running at 7Mhz and in one case, up to 16Mhz - OMFG THE SPEED!!), and i don't see the need to change it - at least not for a preliminary run. They do the job perfectly well, and take up less space than 74LS logic. Thats the purpose of this - not to modify it for FPGA's or PLCC's - two PGA sockets is enough, i think. How about we get the ORIGINAL DESIGN working properly first, and *THEN* we can faff about with improving on it. To start screwing around now - will get confusing.

The 4-layer PCB is a change we can make with ease because it simplifies board routing, cuts down on the noise, and doesn't affect the schematic one iota.

Add the caps back in on the schematic, and it'll be fine.
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Old 11 May 2011, 12:59   #33
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So i will try to solve problems with Eagle this weekend - older version offer AFAIR 160x100mm 2 layer PCB so i will try to create 2 layer PCB (all missing part will be added - decoupling caps can be added even on PCB made from schematics without caps - just on pin and GND)
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Old 11 May 2011, 13:25   #34
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Pandy - If you can sort out the schematic, save it and email it back to me, i can do the PCB work, as i'm not limited in the number of layers, or the size of the PCB

Can you see in the PDF where the FRANCES connector is supposed to go, pinwise??
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Old 11 May 2011, 17:25   #35
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Kai - if i change something in schematic i will send schematic to You.
Autorouter in Eagle is quite limited - not sure how good idea is use autorouter even on 4 layer PCB.

I saw Frances schematic but to be honest not analyzed this to much - from my point of view some replacement for FRANCES must be made - maybe integrated DRAM controller with all PAL integrated too which means new accelerator...
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Old 11 May 2011, 18:13   #36
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The routing i did above, is taking the GND and VCC layers into account, made things a lot easier & simpler, saved a few dozen traces on the board! I was using an 8mm routing grid as well, Gold Phoenix has a minimum requirement of 7mm, and 10mm was too damn big.
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Old 22 May 2011, 16:00   #37
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...any progress, Pandy?
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Old 22 May 2011, 22:19   #38
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Sorry Kai, have no time - unexpected mess in my company - to be honest i have no time even to scratch my b**t - sorry - i was able only to find time to solve Eagle issue.
Anyway i will try to start some work maybe this week but ... work have priority.

Update:

Kai, sorry for next 4 - 5 week I'm out of time - on end of June - beginning of July i should have more time - I've started some PCB however this is very early and far from finish. Sorry once more but project in my company is in serious troubles.

Last edited by pandy71; 30 May 2011 at 01:28. Reason: status update
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Old 31 May 2011, 23:15   #39
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Thats fine dude - there's no rush - i have two projects on the go here - a full engine rebuild on my car, and then an FPGA project that i've been working on for 18 months!

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Old 01 June 2011, 00:57   #40
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So almost exactly like in my case, 2 untouched FPGA boards from Digilent (i've started think to learn VHDL/Verilog on my 40th birthday however i stuck somewhere trying to create Xilinx environment), need rebuild whole suspension in my car in next few weeks and i have almost failed project in work which need to be rescued before complete fiasco...
no holidays up to october
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