01 August 2014, 13:31 | #161 |
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Please, step by step instruction. "Boot with config <config file>, change option a and b using GUI, speed is weird and it seems to hang" or similar.
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01 August 2014, 13:32 | #162 |
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When using BPPC config in latest Beta 8 test zip in SysInfo got allocated memory space 15MB on $68xxxxxx and 16MB on $08xxxxxx ?! (w/o and also when using MapROM)
(seems it happens from beta 5 but didnt it noticed till now) p.s. Btw. The easiest way to enter into BPPC/CSMK3/CSPPC boot menu is to watch power led and in moment when it lit quick press/release Esc key and then keep depressed until boot menu shows. EDIT: Seems there is still problem with BPPC saving changes after changes in boot menu (use, save) ?! Manage to do it once today but now, even when renaming new flash, got corrupted unworking flash ?! (WinUAE beta 8 test zip) Last edited by amilo3438; 01 August 2014 at 13:57. |
01 August 2014, 14:24 | #163 |
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Quickest way to reproduce:
- load A4000/030 quickstart config - load workbench - enable CE in GUI - run sysinfo, run speed test previous releases: test completes with a brief hang reporting CPU speed of 29.. normal behavior (see pic 1) beta 8: test freezes during "computing mflops" for a huge amount of time then reports abnormal speed of 16.. or freezes indefinitely. Both times I tried this with quickstart it froze forever (see pic 2) |
01 August 2014, 14:59 | #164 | |
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Quote:
EDIT: This is only happening when using "Fastest possible" option with CE. Last edited by Snake79; 01 August 2014 at 15:12. |
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01 August 2014, 15:08 | #165 |
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No problems here with such a quickstart config and jump from fastest possible to Cycle Exact - using this latest Winuae Zip File here http://www.winuae.net/files/b/winuae.zip and one of the ClassicWBP96 hardfiles in combination with OS31
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01 August 2014, 15:35 | #166 | |
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Quote:
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01 August 2014, 16:15 | #167 | ||||
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Quote:
Quote:
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Quote:
http://www.winuae.net/files/b/winuae.zip |
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01 August 2014, 16:22 | #168 |
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Ok, after finally being able to get that hang/freeze with the Cloanto OS3X wb files too, this new Zip solves the problem
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01 August 2014, 17:10 | #169 |
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BPPC -> still after boot menu update got unusable file?! (attached below, unzip and rename it!)
(on a new 256k file just enter into boot menu and click on use, save - dont change anything - change to MapROM only and click on use, save) (p.s. On 1st case got working 512 file and on 2nd got unusable file!) Last edited by amilo3438; 01 August 2014 at 21:35. Reason: Attachments probably not needed anymore. |
01 August 2014, 17:32 | #170 | |
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When I enable CE via the GUI, if 'fastest possible' was set it automatically switches to 'approx a500/a1200 cycle exact speed'. Maybe fastest possible was still on and GUI was displaying incorrectly? That winuae.zip has fixed it though, no hang & speed back up to 29 Last edited by vagrant; 01 August 2014 at 17:38. |
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01 August 2014, 18:16 | #171 |
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Doh! That Blood Money sound problem is back with the new winuae.zip.. (sorry tony )
beta 8 -the game works 100% every time winuae.zip - title music is always half speed and small gfx glitch briefly on the ship during intro (see pic). |
01 August 2014, 18:40 | #172 |
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I don't think I really care, it is 68020+ cycle exact which isn't accurate enough and works accidentally only and I also don't really like using whdload games for any kind of compatibiity testing because for obvious reasons slave programmer can't test it with all kinds of configurations.
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01 August 2014, 18:44 | #173 |
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Second PPC status report:
PearPC CPU core does work. Instructions are executed, it does some poking to board's IO addresses but unfortunately I am not sure how addresses F60030 and F60038 work. Only available information comes from netbsd and linux sources: /* IPL_EMU 0x30 */ #define P5_DISABLE_INT 0x40 // if set: all CPU interrupts disabled #define P5_M68K_IPL2 0x20 #define P5_M68K_IPL1 0x10 #define P5_M68K_IPL0 0x08 #define P5_PPC_IPL2 0x04 #define P5_PPC_IPL1 0x02 #define P5_PPC_IPL0 0x01 #define P5_IPL_MASK 0x07 /* INT_LVL 0x38 */ #define P5_LVL7 0x40 #define P5_LVL6 0x20 #define P5_LVL5 0x10 #define P5_LVL4 0x08 #define P5_LVL3 0x04 #define P5_LVL2 0x02 #define P5_LVL1 0x01 Something to do with interrupts but are they input or output or both? Mainboard inputs? Does writing cause interrupts? What? But at least BPPC now boots to amigados and PPC CPU is stopped quite soon after it has been started. Memory is currently directly accessed from PPC thread and all IO addresses are put to queue that m68k side handles and replies. Not very optimal but only way to make it work without extra complexity. |
01 August 2014, 19:16 | #174 | |
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If you get two "OK"'s (at least on CSPPC) then your PPC is alive. EDIT: Note: But WarpOS could be problematic to test on BPPC because of ... just reminds. Last edited by amilo3438; 01 August 2014 at 19:56. |
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01 August 2014, 19:27 | #175 | |
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01 August 2014, 19:49 | #176 |
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But could disassemble CSPCC you have, right ?! ... piece by piece and compare.
(p.s. Didnt you already mentioned somewhere you still have one?) Nobody said it would be easy, but it would be a real shame to give up now. On some sites it already seen as a done deal -> http://www.indieretronews.com/2014/0...pc-update.html In any case, you'll know the best is it worth the effort/trouble. Last edited by amilo3438; 01 August 2014 at 20:21. |
01 August 2014, 20:24 | #177 | |
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Also src/sys/arch/amigappc/amigappc/locore.S and maybe src/sys/arch/amigappc/amigappc/machdep.c |
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01 August 2014, 20:39 | #178 |
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It does not tell if PPC can cause m68k interrupt by writing to those registers or if it can be only used to read m68k interrupt level and to set virtual PPC interrupt level.
Netbsd/Linux does not need to care about m68k after switching to PPC. EDIT: also function of "P5_ENABLE_IPL" is not that clear.. Last edited by Toni Wilen; 01 August 2014 at 20:45. |
01 August 2014, 20:41 | #179 |
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01 August 2014, 20:46 | #180 |
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No but there has not been any compatibility improvements in this beta, nothing has really happened except support for "fastest possible cycle exact" mode. Which obviously has nothing to do with compatibility
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