Creating a new 020 accel board for A600 (eventually to A500 too)

[Hungry Horace]

although Zetr0 lovingly answered many of my questions via PM, i remain unsure.... how is this going to connect? via the trapdoor slot?

if so, what does that mean for those wanting 2 meg of chipram in their a600s?


and i cant find that 2 meg chipram expansion with clockport anywhere (if thats how the expansion may connect). amigakit seem not to have it anymore

[Fingerlickin_B]

A: I'm not sure that it actually could connect via the trapdoor edge.

B: I certainly hope it doesn't! My PPC card is already connected there!

PZ.

[Zetr0]

The Expansions planned all connect to the 64 pin CPU socket of the A500 or Clip over chip the CPU in the A600.

for A600 clock ports there are two options that I know of, both from Jens

the A602 (1mb chip + RTC + 1 clock port)
the A600 Interface Expander (connects to cpu)

[Zetr0]

Looking at gens designs the clock port looks quite passive, infact it should be easy enough to create a very simple board that would provide a clock port.

@Hungry Horace
so what mischief have you planed for your A600's clock port?

[Hungry Horace]

@Ztero - none, now i know this doesnt need it!

anyone got any old a600 chipram expansion for sale?

[kolla]

I really dont grasp why anyone would want or need anything more than an SD/MMC-card slot or two, considering the price/availability of memory cards these days - I just got two 8GB cards for close to nothing. Ofcourse an SD/MMC card slot is basicly IDE, so I guess adding a 40 pin header for IDE is not much extra.

But SCSI? Nah.
What do people want to hook up, old, noisy hard drives?

Btw, the other day I found something funny in my local computer store - 40pin IDE to SATA adapter - hook 2 SATA devices to regular 40 pin IDE header, no special drivers needed

https://www.mamoz.no/produkt/170567/...SATA_disk.html

[Zetr0]

@Kolla

hello there, a most interesting link, i have been fishing around for one, actually a couple of these, how much is that via that link ? (in GBP / Euro)

A friend and I have been toying with SATA and the thought of eSATA devices hooked up to a miggy

As much as in the most part i do see the point of WHY SCSI when IDE is simpler, cheaper etc.

Well it all comes down to CPU load, IDE on the amiga, is infact PIO 0 and eats cpu cycles and essentially slows down the cpu considerably!

SCSI on the other hand is managed by a controller freeing up the CPU, this drasically speeds up even the slowest CPU -> Backing store times . with the right kinda of development a small implementation of DMA could be incorperated with the SCSI controller and this improves performance even further!

to give a rough idea PIO mode 0 IDE will max out at 2MB per sec with an 060@50 behind it.. (at this the 060 wont be able to do anything else as it has to wait, fetch and wait some more)

a 20mhz FPGA SCSI controller will max out around 4MB per sec with a 68000 chip requesting it. with the implementation of DMA this will increase seek / request speeds from chip to controller and improve around 25 - 33%, with a faster controller well speeds upto 40MB a sec are possible with NO overhead for the CPU.

all this being said the first implementations will have IDE, for simplicity

[rkauer]

Originally Posted by Zetr0

--zip--

all this being said the first implementations will have IDE, for simplicity

Note the A600 accelerator will "lack" this feature for obvious reasons!

[Zetr0]

LOL

indeed

[FrenchShark]

Hello,

just an update : I ran the TG68 compilation on Quartus II with a cyclone III EP3C10E144C7. It takes 3000 LEs (out of 10320) and the Fmax is 22.85 MHz.
We may expect a 6x speed increase with a FPGA.

Regards,

Frederic

[Zetr0]

Impressive...

It still surprises me how far these chips have come...

[Hungry Horace]

arrgh, i wish this thread hadnt started!

i am getting impatient for this awesome expansion already!! can i pay in advance?!

rkauer - just two more weeks yeah??

[rkauer]

Originally Posted by FrenchShark

Hello,

just an update : I ran the TG68 compilation on Quartus II with a cyclone III EP3C10E144C7. It takes 3000 LEs (out of 10320) and the Fmax is 22.85 MHz.
We may expect a 6x speed increase with a FPGA.

Regards,

Frederic

@ Fredie:


Sounds impressive, but a real "full" 020 or 030 @ 25MHz plus some RAM and we achieve the very same result. I wonder if a simpler FPGA can achieve the same speed (like those 3128 Z sent me ). 6x speed (compared to 68000@7MHz) is normal with a humble 020 with fast RAM.

So back to the real 68k...sigh...

But nothing impending anyone to use this into a large (and faster) FPGA to a future accelerator, if the price is right. Today a decent FPGA costs much more than the original CPU, with one major drawback (I hate militarism, don't you?): you need to upload the firmware before the chip start to act like a real CPU .

[rkauer]

Originally Posted by Hungry Horace

arrgh, i wish this thread hadnt started!

i am getting impatient for this awesome expansion already!! can i pay in advance?!

rkauer - just two more weeks yeah??

Yeah, two more weeks (tm)

BTW: no pre-orders until we have a real product in hand. And the board will be achievable in an eagle file to anyone who wish to make his own accelerator. Mounted units from the authors, of course, with a little payment for the hand work.

[Hungry Horace]

that's very admirable waiting for the product to emerge... but doenst help my patience!

and make my own?? fat chance! worth the extra cost to let someone 'less dodgy' than myself do it

[FrenchShark]

Originally Posted by rkauer

@ Fredie:


Sounds impressive, but a real "full" 020 or 030 @ 25MHz plus some RAM and we achieve the very same result. I wonder if a simpler FPGA can achieve the same speed (like those 3128 Z sent me ). 6x speed (compared to 68000@7MHz) is normal with a humble 020 with fast RAM.

So back to the real 68k...sigh...

But nothing impending anyone to use this into a large (and faster) FPGA to a future accelerator, if the price is right. Today a decent FPGA costs much more than the original CPU, with one major drawback (I hate militarism, don't you?): you need to upload the firmware before the chip start to act like a real CPU .

Cost more, are you sure ?
68EC020AA25 : $25 (Future Electronics) even if Freescale said $15, I could not find it at this price.
EP3C10E144C7 : $21 (Digikey)
EP3C5E144C7: $15 (Digikey)
EP3C5E144C8 : $12 (Digikey)

The firmware is put inside a serial EEPROM and is loaded automatically by the Cyclone III at bootup time. The loading time is about 100 ms.
With 10,000 LEs you can have a 68000, a DSP, a SDRAM controller and IDE controller and some audio outputs (1-bit DAC technology).
Just a reminder : the DE1/DE2 minimig fits into 12,000 LEs (68000 + OCS chipset + Z80 as floppy emulator)

Regards,

Frederic

[rkauer]

Originally Posted by FrenchShark

Cost more, are you sure ?
68EC020AA25 : $25 (Future Electronics) even if Freescale said $15, I could not find it at this price.
EP3C10E144C7 : $21 (Digikey)
EP3C5E144C7: $15 (Digikey)
EP3C5E144C8 : $12 (Digikey)

The firmware is put inside a serial EEPROM and is loaded automatically by the Cyclone III at bootup time. The loading time is about 100 ms.
With 10,000 LEs you can have a 68000, a DSP, a SDRAM controller and IDE controller and some audio outputs (1-bit DAC technology).
Just a reminder : the DE1/DE2 minimig fits into 12,000 LEs (68000 + OCS chipset + Z80 as floppy emulator)

Regards,

Frederic

Yeah, I know those prices, but we need the serial EPROM, too. And they don`t come cheap, I'm afraid.

Plus we need some level shifters to raise the CPLD voltage level (3.3V) to IDE level (5V). Yeah, some optocouplers can do this job (one for each IDE signal, since GND is GND, anyway), but the final price is going bigger and bigger.

Using a CPLD to control SDRAM memory is good idea, and will be implemented. If you want, I have a PPC DDR/SDRAM interface in verilog code to start some tweaking to adapt it to 68k code/behaviour. It uses one small Cyclone to achieve this. For today, I'm thinking in ordinary SIMM interface (inexpensive, no need for huge CPLD to control it).

The balanced price/performance is important. If we can achieve a great update using inexpensive solutions, that will be the way. That`s why I'm looking for an old SDRAM DIMM controller in CPLD (didn't find one 'till now ). Those not-so-old technology can be used in a 68k accelerator without major re-designs on the memory controller, using a small 5V CPLD/FPGA/GAL. Those DIMM modules usually comes with 64~256Mb and 10ns cycle (very good to interface with a 68k, in my opinion).

Oh, and for 68k CPU, we can always catch some on fleabay or even on old hardware. This accelerator will be a hobby project, at least at start! ROHS compliant will be an issue in Europe, I know...

[Zetr0]

@FrenchShark

You love the FPGA dont you... its okay.... i do too

The prices for 68ec020fgxx are a lot cheaper when you know some one with a large stock of them

say..... about 200 units

[TheCorfiot]

Originally Posted by Zetr0

@FrenchShark

You love the FPGA dont you... its okay.... i do too

The prices for 68ec020fgxx are a lot cheaper when you know some one with a large stock of them

say..... about 200 units

Well thats 200 accelerators in the pipeline then

Give me a REAL 680xx any day

[FrenchShark]

Originally Posted by rkauer

Yeah, I know those prices, but we need the serial EPROM, too. And they don`t come cheap, I'm afraid.

Plus we need some level shifters to raise the CPLD voltage level (3.3V) to IDE level (5V). Yeah, some optocouplers can do this job (one for each IDE signal, since GND is GND, anyway), but the final price is going bigger and bigger.

Using a CPLD to control SDRAM memory is good idea, and will be implemented. If you want, I have a PPC DDR/SDRAM interface in verilog code to start some tweaking to adapt it to 68k code/behaviour. It uses one small Cyclone to achieve this. For today, I'm thinking in ordinary SIMM interface (inexpensive, no need for huge CPLD to control it).

The balanced price/performance is important. If we can achieve a great update using inexpensive solutions, that will be the way. That`s why I'm looking for an old SDRAM DIMM controller in CPLD (didn't find one 'till now ). Those not-so-old technology can be used in a 68k accelerator without major re-designs on the memory controller, using a small 5V CPLD/FPGA/GAL. Those DIMM modules usually comes with 64~256Mb and 10ns cycle (very good to interface with a 68k, in my opinion).

Oh, and for 68k CPU, we can always catch some on fleabay or even on old hardware. This accelerator will be a hobby project, at least at start! ROHS compliant will be an issue in Europe, I know...

The EPCS1 is at $3.50 but because of speed issue with the Cyclone III(the EPCS1 is too slow for the cyclone III), it might be necessary to use the EPCS4 which costs... $13.
Maybe we can keep the 68000 running for initializing the FPGA then, once the FPGA is ready, it deactivates the 68000 and triggers a reset.

DIMM modules are 64-bit IIRC, you will lose half of their capacity on a 32-bit CPU. You may put buffers/switches to get access to the 64-bit datapath but that won't be cheaper than voltage shifting for FPGA.

Yesterday, I have looked at the different 68000 signals : there are 31 outputs (23 addresses, AS, UDS, LDS, RW, VMA, FC0, FC1, FC2), these need 4 bus drivers like a 74ACT373. Then, there are 16 bidirectional signals (the databus), two 74LVC646 have to be used. Finally, there are 9 inputs (IPL0, IPL1, IPL2, BERR, VPA, RESET, HALT, CLK and DTACK). One CBTD3384 is enough here.

74ACT373 : $0.51 (x 4)
74LVC646 : $1.26 (x 2)
CBTD3384 : $0.64
$5.20 of buffers

To me, the expensive item will be the 4-layer PCB.

Regards,

Frederic