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Old Yesterday, 22:28   #781
roondar
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Quote:
Originally Posted by Don_Adan View Post
I dont coded for long time, and checked my Amiga assembler book again, but add.l ea,Dn takes 6+ cycles, when ea for Dx is equal 0, then 6+0=6c.
Oh, I believe you when you say that your book says it's 6 cycles. However my source (and others) say it's 8 cycles so I'll just say: it's less certain than I thought since different sources disagree.

Which IMHO means the fair solution (given I don't feel like making a test program) is to keep it at 'uncertain', so I'll do that from now on. After all, my source could be wrong, but so could your book.

It's just the way it goes sometimes
Quote:
Originally Posted by meynaf View Post
Don't ask litwr - not his code.

I'm adding address registers to data registers, because i'm out of data registers and therefore some data has to go in address registers.
Using word operations is a bad idea because it's only valid for 68000 (others don't care), adds some constraint on the other function, and - i repeat - this code isn't speed critical.
Thanks for the clarification, like I said I hadn't really followed this part of the discussion much. Personally, I don't completely agree with the part where you say using add/sub.w is a bad idea per se, but I don't feel much like discussing it so I'll drop it. You probably had a reason to do it this way.
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Originally Posted by coder76 View Post
You also can't see performance of a CPU by just looking at cycle counts for each instruction and comparing it against other CPUs . There are other factors, like cache performance, and number of registers available, which are also important for performance. The x86 cycles for instructions seem on paper often impressive, but x86's lacked the amount of CPU registers that 680x0's have. Also, the 386/486 caches weren't as good as 68030/68040's caches (386 had some sort of external cache).
I wholeheartedly agree with this statement, which is part of why I keep saying that comparing tiny bits of code is not going to give a clear answer.
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Old Today, 00:38   #782
frank_b
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Quote:
Originally Posted by coder76 View Post
The x86 cycles for instructions seem on paper often impressive, but x86's lacked the amount of CPU registers that 680x0's have. Also, the 386/486 caches weren't as good as 68030/68040's caches (386 had some sort of external cache).
Only impressive if you forget about the cost of filling the prefetch buffer. The 8086 and 8088 are much slower than they appear to be from Intel's documentation. At least according to the Zen of assembler programming.
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Old Today, 04:44   #783
mc6809e
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This might already be somewhere around here but I thought I'd post it as it seems somewhat relevant:

http://nemesis.hacking-cult.org/Mega...tion/Yacht.txt

Amazing document concerning the cycle by cycle behavior of the MC68K for every instruction and even interrupts.

Very interesting.
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Old Today, 04:48   #784
mc6809e
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Originally Posted by frank_b View Post
Only impressive if you forget about the cost of filling the prefetch buffer. The 8086 and 8088 are much slower than they appear to be from Intel's documentation. At least according to the Zen of assembler programming.
Yeah, you're right, of course.

Terje has said that you could very well estimate the speed of most code by simply counting the total number of memory accesses needed.

Anyone really interested in all this should check out some of the old posts by Terje on that now backwater of the internet, usenet. Check out comp.arch, in particular. Very interesting reading.
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Old Today, 09:11   #785
meynaf
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Quote:
Originally Posted by roondar View Post
Oh, I believe you when you say that your book says it's 6 cycles. However my source (and others) say it's 8 cycles so I'll just say: it's less certain than I thought since different sources disagree.
Doc says 6 but measurement on emulator says 8.
As memory cycles are 4 cpu cycles, it seems logical that instructions execute in multiples of 4 cycles, btw.
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Old Today, 10:37   #786
dissident
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Maybe this little assembler tool will give you some answers regarding execution times on the MC68000.

Back in the days, it was published in the German "Amiga Magazin Sonderheft -Faszination Programmieren" edition 2/93.
It helped me a lot and in conjunction with CIA registers you get really surprising results.

This tool was mainly written for the MC68000, and for other processors of the 68k family you have to change the value for the execution time of an empty loop and perhaps the rounding value. Just play with the values. But no guarantee for a proper work on 68020+ machines, it may be only a kind of orientation because of their caches and pipelining behaviour.

Have fun with it.
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Old Today, 12:11   #787
roondar
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Quote:
Originally Posted by frank_b View Post
At least according to the Zen of assembler programming.
This book turns out to be available online as well. Very interesting read (including the bits about prefetch and how it impacts performance from the theoretical cycle counts), though the author is a total Intel fanboy

In essence, it turns out that Motorola was just more 'complete' with their 68000 cycle numbers because they did include the -admittedly hard coded- prefetch into the cycle counts in their manuals (they also do so -to a point- for the 68020 onwards by explaining best/worst/cache performance and concurrency) where Intel did not*.

Which makes the 68000 look slower than it really is when compared to the Intel 8088/8086, whose cycle counts in the manuals don't include these fetches and thus are regularly slower than stated. Note that all this doesn't mean the Intel cycles as given are dishonest, rather they measure a different thing and as such require a bit more work to get the complete picture.

I am unaware if this situation also occurs for the 286/386/486, but it wouldn't be surprising if the same thing applies. Generally I find that manufacturers don't change their method of reporting specs unless they have a good reason to do so.

*) Considering how complicated this can get I'm not too surprised to be honest, just look at the MC68020 stuff in the Motorola manuals and how unclear the actual performance of individual instructions can get when some cache and internal concurrency is part of the deal.
Quote:
Originally Posted by mc6809e View Post
This might already be somewhere around here but I thought I'd post it as it seems somewhat relevant:

http://nemesis.hacking-cult.org/Mega...tion/Yacht.txt

Amazing document concerning the cycle by cycle behavior of the MC68K for every instruction and even interrupts.

Very interesting.
That is a really interesting document, I'll be saving & using that for sure!
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