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Old 02 July 2018, 22:43   #21
PR77
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Originally Posted by pandy71 View Post
As i said - you will significantly simplify design if you provide own clock to Amiga instead trying to separate pixel clock from video data.
I don't really understand how this will simplify the design. Considering only the LoRes pixel clock, if this same as the CPU clock why can't this be used? Are they at different phases?
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Old 02 July 2018, 23:20   #22
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I don't really understand how this will simplify the design. Considering only the LoRes pixel clock, if this same as the CPU clock why can't this be used? Are they at different phases?
It can be different phase - you should check Gayle datasheet - there is waveforms provided to show all dependencies. Side to this my assumption is that you using video port not hooking wires to pins internally.
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Old 02 July 2018, 23:41   #23
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It can be different phase - you should check Gayle datasheet - there is waveforms provided to show all dependencies. Side to this my assumption is that you using video port not hooking wires to pins internally.
I was actually connected directly to DENISE and the RGB, H+V SYNC and CPU_CLK signals. This design, should I pursue it, would be internal to the Amiga, similar to Indivision ECS.

What signals in the GAYLE data sheet are you referring to specifically?
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Old 03 July 2018, 01:38   #24
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I was actually connected directly to DENISE and the RGB, H+V SYNC and CPU_CLK signals. This design, should I pursue it, would be internal to the Amiga, similar to Indivision ECS.
I see - then OK.

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What signals in the GAYLE data sheet are you referring to specifically?
Check page 10 - video clocks and phase relations between them.
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Old 03 July 2018, 11:40   #25
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Thanks! Have you made something similar yourself? You appear to know quite a lot on this topic.

My PCBs arrived yesterday for my 68SEC000 accelerator so that will take priority (after family and work) and then I will circle back to this at some point.
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Old 03 July 2018, 12:27   #26
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Thanks! Have you made something similar yourself? You appear to know quite a lot on this topic.
Doing some things on this area but decided to not say anything until it will be ready.
Progress is slow due other things with higher priority.

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My PCBs arrived yesterday for my 68SEC000 accelerator so that will take priority (after family and work) and then I will circle back to this at some point.
I need to finish other things first so decided to shift effort on this - but if i can help then i will be happy to do so.
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Old 04 July 2018, 13:49   #27
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I need to finish other things first so decided to shift effort on this - but if i can help then i will be happy to do so.
Thanks. I will be sure to keep you in the loop when I pick it up again. I populated my 68SEC000 accelerator last night and I see about 15 bus cycles then the CPU /HALT is asserted. Something is fundamentally wrong so it might be while before I pick up on the LCD work again. If you are interested in this I can share the details of that also!
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Old 06 July 2018, 18:18   #28
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Thanks. I will be sure to keep you in the loop when I pick it up again. I populated my 68SEC000 accelerator last night and I see about 15 bus cycles then the CPU /HALT is asserted. Something is fundamentally wrong so it might be while before I pick up on the LCD work again. If you are interested in this I can share the details of that also!
Excuse late reply - as i said earlier - other activities has higher priority and also as i said earlier - if i can help then i will be happy to help.
If you face any problem then you should share details on forum - there is many people actively involved in Amiga HW project.
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Old 07 July 2018, 00:27   #29
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I've got my other Thread hear;

http://eab.abime.net/showthread.php?t=89165

However, as it has taken soooooooo long I've lost critical mass! Nevertheless, I will not be defeated!
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