Horizontal split screen with modulo trick

[ovale]

Hello,

I was wondering about how Agnus uses the bitplanes modulo registers to increment the bitplanes pointers.

When, during a scanline, the modulo is added instead of 2?

If it would possible to use the copper to trick Agnus and cause the use of the modulo at a precise place of the scanline the it would be an effective way to implement horizontal split screen.

For example implement a 160+160 pixels split screen requires a 10 words modulo and the two bitplanes rows interleaved in RAM.

By changing the modulo just before it is added it would be possible to fine scroll vertically and coarsely horizontally the 2 sides indipendently.

So, this is the idea and a possible use. Some reverse engineering and tests are required to understand how to trigger the modulo use.

Does anyone already knows how it works (emulators authors and FPGA developers maybe know this) or someone has time to try it out?

Thanks,
Ovale

[Toni Wilen]

Modulos are added, plane by plane, when scan line's last plane words are fetched (after DDFSTOP).

You can restart bitplane DMA after DDFSTOP in same scanline but it only works with ECS (OCS refuses to do it until next scan line) but I don't think it is possible without visible gap.

[ovale]

Originally Posted by Toni Wilen

You can restart bitplane DMA after DDFSTOP in same scanline but it only works with ECS (OCS refuses to do it until next scan line) but I don't think it is possible without visible gap.

Thanks Toni,
How playfield DMA can be restarted on ECS? Maybe this can be a starting point for experiments.

EDIT: typo

[Toni Wilen]

Originally Posted by ovale

Thanks Toni,
How playfield DMA can be restarted on ECS? Maybe this can be a starting point for experiments.

Move DDFSTRT after DDFSTOP (after first DDFSTRT started the DMA). One part in demo Subtle Shades (Nuance) does this. Easy to find by running it in OCS mode

[ovale]

Hi Toni,

On the undocumented features thread you described a DDF state machine with 4 states and hidden temp BPLxDAT registers in Denise.

Is it correct to assume the state machine is updated every memory cycle and therefore the pause in Denise feeding will be 4 cycles?

[Toni Wilen]

They are running all the time (even if all planes are switched off) and even if they would stop, you still can't stop monitor's horizontal scanning. (and result would be Amiga's horizontal counter not matching actual display position anymore)

[Toni Wilen]

I can do some logic analyzer checks with this (to exactly see what cycle does what DMA fetch), perhaps it is possible to adjust DDFSTOP and "new" DDFSTRT exactly right to not cause any gaps. It may even cause some previously unknown side-effect

[ovale]

Cool!

[frank_b]

You can use a similar trick to save loading 8*2 plane pointers at the end of every line. You just need to calculate the relative offset from the line to the line you want to get to, then set the modulo registers. Much faster.

[ovale]

Originally Posted by frank_b

You can use a similar trick to save loading 8*2 plane pointers at the end of every line. You just need to calculate the relative offset from the line to the line you want to get to, then set the modulo registers. Much faster.

Hello frank_b,
Could you further explain your idea and how it is different from what I suggested?

[frank_b]

Originally Posted by ovale

Hello frank_b,
Could you further explain your idea and how it is different from what I suggested?

My idea is only useful for splitting the screen up into multiple vertical chunks.
It requires 16 copper moves to set all 8 plane pointers per line. You can do it in two instead via the modulos.

[ovale]

Got it

[NorthWay]

I'd love to hear if this works with no gap. I've been toying with setting 8 low-word pointers on AGA to get a split with 64K aligned buffers, but this would be so much better. Working on ECS is also interesting.

[ReadOnlyCat]

Originally Posted by NorthWay

I'd love to hear if this works with no gap. I've been toying with setting 8 low-word pointers on AGA to get a split with 64K aligned buffers, but this would be so much better. Working on ECS is also interesting.

This is indeed interesting but excluding OCS means that the stock A500 and A1000 will not have access to that feature.

[Toni Wilen]

Gapless DDFSTRT/STOP horizontal split does not seem to be possible, new DDFSTRT value is ignored until last plane has been fetched after previous DDFSTOP -> It works but there is always a gap.

[NorthWay]

How big is the gap? Is it dependent on the fetchmode? Can it be futzed by changing fetchmode?
(I'm coding something different right now, so I haven't had time to test myself. Yet.)

[ovale]

Maybe the gap can be further reduced by reducing the number of bitplanes or going in hires mode. I mean, just during the gap.

If the Gap is caused by Denise, maybe to write BPL1DAT with the Copper could reduce the gap too.

[Toni Wilen]

Originally Posted by NorthWay

How big is the gap? Is it dependent on the fetchmode? Can it be futzed by changing fetchmode?
(I'm coding something different right now, so I haven't had time to test myself. Yet.)

16 lores pixels. I used ECS A500, I usually don't bother with AGA..

Originally Posted by ovale

Maybe the gap can be further reduced by reducing the number of bitplanes or going in hires mode. I mean, just during the gap.

If the Gap is caused by Denise, maybe to write BPL1DAT with the Copper could reduce the gap too.

Writing to BPL1DAT won't help, it does not affect DMA sequencing (which prevents DDFSTRT detection if "old" bitplane DMA is still active). Changing number of planes or resolution probably won't help because you don't have enough time to switch it back to original and also update DDFSTR in correct positions, without seeing wrong graphics.

What about using tall attached sprite to hide the gap? (But managing the graphics data may get a bit too tricky..)

(Note that horizontal split is possible with copper moves to BPLxPTL if number of planes is 3 or less, 4 would fit but unfortunately won't work due to back to back PTL write/DMA fetch feature preventing it)

[ovale]

Indeed minimize the gap size with hires or lower bitplanes count and cover it with a sprite can be a good compromise.

Even better if would existing a way to switch a bit in a register and force Denise to output color 0. But I'm not aware of such feature. Is it possible?

[NorthWay]

Can someone help with the testing of this? I don't know if my timing is off or what. (AGA 4x)

I tried setting $38/$38, wait, $3a/$9c, wait. Simply testing $38/$38 shows a weird extra fetch in the left hand side overscan. Can you do a display that is only 16(/64) pixels wide? I'm getting the impression it will always do at least two fetches.
My test above ended up looking like it was a regular $38/$9c display of a 320 pixels screen.
What position should I wait for before changing DDFSTART?