First Amiga 600 FPGA Accelerator - Vampire 600

[codeflash]

In other words.. the Dhrystone measure sucks

[matthey]

Originally Posted by codeflash

In other words.. the Dhrystone measure sucks

DMIPS has it's advantages:

1) measures attempted realistic C code
2) it's small
3) it compares performance between different processors

But it also has it's disadvantages:

1) results are too dependent on text (byte) operations
2) it doesn't do any real work and doesn't measure time critical code
3) it's dependent on good compilers to generate good code
4) compilers doing too good of job are considered cheating
5) compilers can completely optimize away large chunks of the code
6) it's too easy to cheat and not well enough defined what cheating is

What are the 68k processors capable of in DMIPS? We will never know. There isn't a good enough compiler to give the results Motorola quoted. I can double the numbers (beyond what Motorola quotes) by hand optimizing trying not to cheat. Dhrystone results are too dependent on the compiler IMO.

[codeflash]

Which points in the direction of measuring real-work(tm) ..
Bonus is that if can cheat on that.. then you accomplished something seriously useful anyway

[matthey]

Originally Posted by majsta

For comparison mc68040

1k 8 MB/s

If our math is correct, a 68040@25MHz should be able to do closer to 18MB/s with 1k element. Were the caches on?

Originally Posted by majsta

Regarding adding different core into my project. I said that it could took me about 2 hours to redesign complete thing for let's say Cyclone 5 or something. it has 115 000 LE or how do they call them those days. But then again lets finish what i have started and for now it seems that I m going nowhere. Today I attached new SDRAM controller completely different than those used before and problems remain. So maybe problems are somewhere else. We will see.

ALM. Would upgrading to a Cyclone 5 make things easier because of the built in memory controller?

[pandy71]

Very good benchmark http://www.fftw.org/benchfft/

[blizz1220]

@MattHey

Originally Posted by matthey

If our math is correct, a 68040@25MHz should be able to do closer to 18MB/s with 1k element. Were the caches on?



ALM. Would upgrading to a Cyclone 5 make things easier because of the built in memory controller?

I have two questions for you Matt ,

1. Please explain nature of Apollo core in a more lamers terms
Such as does it resemble 020 , 030 , is it more like 060 , is it
2 x freq or RISC inside ...

2. Any chance perheps of you finishing it yourself ?

[matthey]

Originally Posted by pandy71

Very good benchmark http://www.fftw.org/benchfft/

It's realistic work, processor intensive, and has results that can be checked for accuracy but it uses floating point (FPU or SIMD).

Originally Posted by blizz1220

1. Please explain nature of Apollo core in a more lamers terms
Such as does it resemble 020 , 030 , is it more like 060 , is it
2 x freq or RISC inside ...

The Apollo is a highly pipelined superscalar 68k CPU. It has 2 integer units like the 68060. It currently runs in simulation at about 150MHz CPU clock speed in a Cyclone 5 giving 68060 level performance. It has a very efficient cache design. It has a 68020 ISA with enhancements like ColdFire instructions. It's a complex mythological creature that may not ever work properly .

Originally Posted by blizz1220

2. Any chance perhaps of you finishing it yourself ?

I am not qualified to finish it. It requires more microprocessor design and VHDL programming skills than I currently posses.

[blizz1220]

Originally Posted by matthey

The Apollo is a highly pipelined superscalar 68k CPU. It has 2 integer units like the 68060. It currently runs in simulation at about 150MHz CPU clock speed in a Cyclone 5 giving 68060 level performance. It has a very efficient cache design. It has a 68020 ISA with enhancements like ColdFire instructions. It's a complex mythological creature that may not ever work properly .

Now that sounds good to me

Originally Posted by matthey

I am not qualified to finish it. It requires more microprocessor design and VHDL programming skills than I currently posses.

Damn

[pandy71]

Originally Posted by matthey

It's realistic work, processor intensive, and has results that can be checked for accuracy but it uses floating point (FPU or SIMD).

Or FPU emulation - i mean float library.

Most of benchmark seem to be not realistic (i doubt how many days spent A4000 doing complex 1Mpts FFT but some selected FFT's perhaps up to 64kpts should be usable as a universal benchmark (additional limitation can be memory footprint).

[majsta]

Ok we have it definitely. Remember those are testing without any cache added so performance with 3 point something Mips are amazing because without cache I didn't get more than 2.64 Mips. So adding cache now is trivial thing and code is prepared and ready. Core runs now at amazing 100MHz. Now auto config option working. I added only 8MB of memory and rest up to 64MB will be added soon. Now all tests are passed, everything seems normal to me, system is fast and stable. Since I have received information from minimig community that every time they need to test new core compilation they run Zeewolf2 test so if that game is started everything is fine because game is too much sensitive on partially or non working FastRAm. So here is little video and from me only one thing I can state again. I m persistent and maybe most stubborn person you may know and when I say to myself that I will enter into some project I will finish it no matter what. And here is definite prove that you don't need to have money, knowledge or any background experience only simple "yes I can" will be enough.

[ Show youtube player ]

[kipper2k]

Awesome achievement, well done, do you think you can fix the youtube video

edit... video working now.

[Lord Aga]

Way to go Majsta Achieving all this from scratch is a real feat !

[kipper2k]

What do you think sysinfo will show once up and running with everything optimized ?

[majsta]

@kipper2k heh like you notice I don't care too much about quality of published videos and pictures
@Lord Aga yes I m somehow proud to myself and if I may say I had great moral support from you and other enthusiastic people from Balkans

What is left to do, only few tweaks and I have no idea how much this can go regarding performance but it will be stable at 6Mips that is for shore. If I could achieve anything above that it would be nice.

@kipper2k I just don't know how much I can accomplish but it is not important right now. Most important thing is to get this produced and later on with core updates we can expect more and more. I started to work with another cache with some different approach and maybe just maybe we will have 060 performance but I can't promise that it is all in theory.

[kipper2k]

Originally Posted by majsta

@kipper2k heh like you notice I don't care too much about quality of published videos and pictures
@Lord Aga yes I m somehow proud to myself and if I may say I had great moral support from you and other enthusiastic people from Balkans

What is left to do, only few tweaks and I have no idea how much this can go regarding performance but it will be stable at 6Mips that is for shore. If I could achieve anything above that it would be nice.

Yah, the video was a little fuzzy, i did clean off my glasses but it didnt help lol

[majsta]

Went to drink coffee. To clear my mind.
Little recompile. System stable running at 6.34Mips, chip speed vs. A600 2.67. Everyting damn,damn fast. Zeewolf 2 started without any problems. Lets try to increase freq up to 166MHz and see what happens.

[protek]

Awesome work!
Yes you definitely can.

[kipper2k]

if 6.34mips = 100mhz, does 166mhz = 10.55mips?

[majsta]

Yes 6.34 Mips are accomplished at 100MHz with cache and those 3 point something Mips are accomplished also at 100MHz but without cache.

[kipper2k]

loverly, heres hoping. mabbe we should set up donations for a new video camera for you