29 June 2017, 18:17 | #241 | ||||
son of 68k
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It is not 1980s technical arguments. I will try to ignore this. Quote:
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Apparently not, as more are open all the time |
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29 June 2017, 18:26 | #242 |
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Because today's machines run multi-processor multi-threading operating systems and can put an additional CPU core to better uses than just copying data around. Not an 1980s technical argument?
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29 June 2017, 18:41 | #243 |
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Adding to this, the Intel i-series uses both multicore and hyperthreading techniques. A quad-core i3 has eight threads.
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29 June 2017, 18:53 | #244 |
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That is one reason - the main reason is still memory-bandwidth. You want your CPUs to do as few memory operations as possible, since moving something that is not in cache is still horribly slow. The problem increases of course with more cores/threads.
Last edited by Gorf; 29 June 2017 at 19:02. |
29 June 2017, 19:01 | #245 | |
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For just one specific task, there is not so much difference: you can use a DMA to offload the work or a second CPU. But since hyper threading does not exactly double your speed, you will slow down the other thread a little bit while doing so. It becomes more complicated if you want to offload more than one task. You can have a dedicated DMA-controller for each purpose und things will get done without bothering the CPU. If you want to do different DMA-tasks with one thread of your HT-CPU ... well than you end up needing a extra scheduler for this or some support in the OS or both. |
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29 June 2017, 19:02 | #246 |
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@Overflow:
Thanks for post #215 How does Vampire/Apollo IDE work? How much CPU time is used? Isn`t the CPU much to slow to have fast IDE? My FastATA A1200 uses nearly all CPU time to be "fast" (~8MB/sec.). As far as I`ve heard the old DMA or UDMA standard don`t use much CPU time. Will the standalone get a decent SATA controller so we get standard transfer speed? MMU is a basic part of most 68k CPUs (030, 040, 060). Apollo is or will be 680x0 compatible. Hence it isn`t unusual to assume ther will be one. Same goes for FPU but later nothing is promised after people noticed and asked. What you get is only a gift is the answer. Of course this leads/spawns to discussions. @OlafSch: What is an MMU application or what do you think what it is? As far as I know MMU is a hardware unit/technic (kind of layer between CPU and memory) that can be used or not. So application can only make use of it. You can program MMU direct or use mmu.library to access it. So MMU application does not exists. That a MMU slows down much I can`t confirm. In fact I don`t notice it with 040/40 and mmu.library/MuForce running. If a MMU unit slows down Apollo core much then the FPGA is two small/slow or the design is not good enough and would need improvement/changes. Overall I`m the opinion that speed is not everything. If someone says that MMU is only useful for developers than it is wrong. Maybe I`m the only one but I`m not a developer but use tools that make use of MMU. |
29 June 2017, 19:15 | #247 |
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About the Hyper-Thingy
I don't think HT on Apollo/Vampire is a bad idea. I fact I was asking for more cores in the fpga myself. HT is at least a small step towards more cores. What for? For one there is AROS-SMP, that might possibly be adapted ... once it is working stable enough. And there is Sandboxing. But of course this would need a exposed MMU. But than it would allow to run something like a second instance of Exec in a Sandbox on the second core - very nice for development and testing, but also for security. But this wish was low priority - FPU and MMU would have been much more important I think. Sure, this is up to Gunnar - but I can understand that some people might be a little disappointed. |
29 June 2017, 19:26 | #248 |
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I see no reason why sandboxing would need a second core ?
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29 June 2017, 19:27 | #249 |
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29 June 2017, 19:34 | #250 |
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You are right of course. I just needs a MMU.
But it would be also a way to make use of a second (or more) cores on AmigaOS, without braking compatibility: Take a raytracer or a decoding datatype and offload portions of task to different sandboxes and cores - fetch the data when finished. |
29 June 2017, 19:37 | #251 | |
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Mostly developer stuff, not stuff one would notice as a user/gamer.
http://whdload.de/docs/en/mmu.html Quote:
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29 June 2017, 19:40 | #252 | |
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If you get lucky, the protection the MMU offers, will allow you to recover from a crash within whdload without rebooting. |
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29 June 2017, 20:05 | #253 |
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Well, the 080 core has normal DMA (start address, destination address, number of bytes, pull trigger, go) already in case facts about the present state are of any interest here. DMA should go through the cache for coherency such that there is again no real difference when comparing to a second CPU. Just try to see the 2nd thread as a flexibly programmable DMA controller and one that uses all resources that are currently not used by the main thread: it's completely for free! You could also use it as a software blitter doing pixel format conversion on-the-fly and much more.
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29 June 2017, 20:24 | #254 |
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What happens if both threads need the same resource at the same time ?
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29 June 2017, 20:31 | #255 | |
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On a real second core it would occupy some memory bandwidth - so you have to code and schedule things very carefully, so nothing gets slowed down. This is a problem you can observe on every multicore system out there. It gets worse if you just have two virtual cores through hyper-something: the second thread will slow down the first one, since not everything can be absorbed just by a multiscalar design. |
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29 June 2017, 20:35 | #256 |
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29 June 2017, 20:41 | #257 |
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That does not help if, and this is the common case, both threads need the same functional units in the core.
These units are of course limited - there may even be some redundancy on an multiscalar CPU, but once all the units needed are assigned to the operations in the pipeline: one thread has to wait. Last edited by Gorf; 29 June 2017 at 20:48. |
29 June 2017, 20:52 | #258 | |
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29 June 2017, 20:54 | #259 |
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That said, I've never encountered any hard crashes or reboots with WHDload on any of the games I've played on my Vampired A600. Of course haven't tried any AGA games yet, waiting for the Gold 3 core for that.
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29 June 2017, 20:54 | #260 |
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Short: Meynaf is right,
Long: DMA can provide time deterministic response for time critical event which is usually beyond capabilities of the modern CPU's (unless special CPU's design) nowadays DMA are usually provided with basic data processing (so they can be considered as special case CPU) - they can even assist decoding for modern video codecs such as H.264 or detect particular bitstream errors (classical examples are DMA channels frequently called FDMA - Flexible DMA in modern multimedia players SoC's). With clever (proper) system design - DMA may use cycles wasted by CPU or may use available bus time significantly more efficient than CPU. General CPU usually perform code with lot of conditional cases where DMA is usually block oriented wit relatively simple data flow (without conditional or conditional are highly limited - error detection etc). DMA can be emulated by CPU but usually at a cost of additional cycles. Bus access is always problem as such you need good architectural design for any concurrent access arbitration (so good bus arbiter is crucial from overall system performance perspective). Good illustration for this is general trend in modern CPU's (those with long queue length) is to avoid interrupts in a favor of pooling... |
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