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Old 09 May 2020, 06:41   #1
PurpleMelbourne
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Question Replacing PALs with CPLD to the A2630 for Rev 10 open design

I've been wanting to learn programmable logic and it occurred to me that updating the A2630 from old PAL's to CPLD would be useful to our beloved community.

I'm hoping someone on this forum might explain how to view, edit and convert the .PLD files to program suitable CPLD replacement such as Xilinx XC95288XL.

A2630 looks like a great learning tool for learning digital electronics of the Amiga. Perhaps educational tool could become a new niche for Amiga?

From what I understand, the first number is the total number of io's available and the second number is the availble outputs availble out of that total number.
So 20R4 is a total of 20 io's which is maximum of 4 outputs which would leave 16 inputs.

The PALs are:
1 x 20R4
5 x 20L8
4 x 16L8
2 x 16R6
1 x 16R4

6x20 + 7x16 = total io of 120+112 =232 io's
1x4+5x8+4x8+2x6+1x4 = 92 outputs

140 inputs and 92 outputs
Many outputs feeding back to other PAL's.

Currently manufactured Xilinx XC95288 with 208 pins has 168 io pins, sounds like a good replacement chip.
https://www.xilinx.com/support/docum...eets/ds055.pdf

Those PAL's mostly convert the 68000 control signals of the motherboard to the 68030 control signals used by the cards new CPU, but also A2630 has 4MB autoconfig FAST RAM which notably is still accessible to the 68000 when the 68030 is disabled!

The memory controller is here in its logic form which is good for looking at to see how these things work. It's fascinating to see on first page how 18 bits of CPU address lines get multiplexed through 74F257 logic chips to make 9 bits RAM chip address lines plus CAS and RAS signal lines in the RAM chip method for addressing.

This A2630 schematic is a great document for learning how digital electronics works

A2630 AmigaWiki : https://www.amigawiki.org/doku.php?i...sion:cpu:a2630
Engineer notes -- : http://www.devili.iki.fi/mirrors/hay...rbd/readme.txt
Schematics ------ : https://www.amigawiki.org/dnl/schematics/A2630_R9.pdf
A2630 PALs 1 ---- : http://www.devili.iki.fi/mirrors/hay...ds/a2630/pals/
A2630 PALs 2 ---- : http://www.devili.iki.fi/mirrors/hay...s/a2630/dtrbd/
Update PALs ----- : http://www.devili.iki.fi/mirrors/hay...ch/a2631/pals/
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Old 09 May 2020, 12:18   #2
hooverphonique
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Quote:
Originally Posted by PurpleMelbourne View Post
So 20R4 is a total of 20 io's which is maximum of 4 outputs which would leave 16 inputs.
The 20 pin PALs (20xy) all have 10 inputs and 8 outputs. "R4" means that 4 of the outputs are registered (has a flipflop). An "L8" has no registered outputs.

Quote:
Originally Posted by PurpleMelbourne View Post
It's fascinating to see on first page how 18 bits of CPU address lines get multiplexed through 74F257 logic chips to make 9 bits RAM chip address lines plus CAS and RAS signal lines in the RAM chip method for addressing.
All common DRAMs work in this fashion
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Old 11 May 2020, 05:56   #3
PurpleMelbourne
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Quote:
Originally Posted by hooverphonique View Post
The 20 pin PALs (20xy) all have 10 inputs and 8 outputs. "R4" means that 4 of the outputs are registered (has a flipflop). An "L8" has no registered outputs.
That's good news. Even less io to worry about

Can you tell me how to view and edit the .pld files that make up the A2630 PALs?
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Old 11 May 2020, 07:36   #4
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Quote:
Originally Posted by PurpleMelbourne View Post
Can you tell me how to view and edit the .pld files that make up the A2630 PALs?
They are just text documents containing header, comments and the logic description language code. I think it is written in PALASM
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Old 11 May 2020, 11:01   #5
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As an utter rank amateur with zero experience but mildly interested enough to look they look fairly straightforwards along with decent amounts of comments.

Code:
/**  Inputs  **/

PIN 1		= !CSAUTO	;	/* Autoconfig chip select */
PIN 2		=  MEG4		;	/* Are we a 4 meg board? */
PIN 3		= !DS		;	/* Data Strobe */
PIN 4		=  PRW		;	/* Processor read write */
PIN 5		= !BOSS		;	/* Indicates that we are the boss ! */
PIN 6		= !CPURESET	;	/* The cpu reset line */
PIN 7		=  CONFIGED	;	/* The board is ROM configed */
PIN 8		=  RESENB	;	/* Enable for CPU reset feedback */
PIN 9		=  A1		;	/* Address line 1 */
PIN 10		=  A2		;	/* Address line 2 */
PIN 11		=  A3		;	/* Address line 3 */
PIN 13		=  A4		;	/* Address line 4 */
PIN 14		=  A5		;	/* Address line 5 */
PIN 23		=  A6		;	/* Address line 6 */
PIN 21		=  OSMODE	;	/* Which OS do you prefer */

/**  Outputs  **/

PIN 15		= !D31		;	/* Data line 31 */
PIN 16		= !D30		;	/* Data line 30 */
PIN 17		= !D29		;	/* Data line 29 */
PIN 18		= !D28		;	/* Data line 28 */
PIN 19		= !ROMCLK	;	/* Rom control register clock */
PIN 20		= !RAMCLK	;	/* RAM control register clock */
PIN 22		=  RESET	;	/* System Reset */
I don't understand what they're doing (although I can guess at some of it) but that's because I don't understand the language. It's not PALASM but I couldn't find what it _was_.
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Old 11 May 2020, 11:17   #6
Fastdruid
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Quote:
Originally Posted by alexh View Post
I think it is written in PALASM
It's not. I had a look at the manual for PALASM

http://bitsavers.trailing-edge.com/c...ware_Jul87.pdf

As an example if in PALASM this code

Code:
PIN 1		= !CSAUTO	;	/* Autoconfig chip select */
PIN 2		=  MEG4		;	/* Are we a 4 meg board? */
PIN 3		= !DS		;	/* Data Strobe */
PIN 4		=  PRW		;	/* Processor read write */
PIN 5		= !BOSS		;	/* Indicates that we are the boss !
would be something like this (I'm not too sure about the ! but you get the idea).

Code:
; PINS 1     2    3   4   5
     !CSAUTO MEG4 !DS PRW !BOSS
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Old 11 May 2020, 12:11   #7
hooverphonique
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I'm not sure, but the file extension and the 'PIN..' syntax could indicate that the source file is for atmel WinCUPL.

Sprint PLDASM also uses a .pld extension, but I couldn't verify the language syntax.
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Old 11 May 2020, 13:10   #8
Fastdruid
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Quote:
Originally Posted by hooverphonique View Post
I'm not sure, but the file extension and the 'PIN..' syntax could indicate that the source file is for atmel WinCUPL.

Sprint PLDASM also uses a .pld extension, but I couldn't verify the language syntax.
Could well be CUPL, from the reference here http://ee-classes.usc.edu/ee459/libr..._Reference.pdf there is an example "template" which looks to be the same format...or an evolution of it at least taken into consideration that the reference manual is from 2012 and the code from 1988!

Code:
Name XXXXX ;
Partno XXXXX ;
Date XX / XX / XX ;
Revision XX ;
Designer XXXXX ;
Company XXXXX ;
Assembly XXXXX ;
Location XXXXX ;
/***************************************************************/
/* Allowable Target Device Types : */
/***************************************************************/
/** Inputs **/
Pin = ; /* */
Pin = ; /* */
Pin = ; /* */
Pin = ; /* */
/** Outputs **/
Pin = ; /* */
Pin = ; /* */
Pin = ; /* */
Pin = ; /* */
/** Declarations and Intermediate Variable Definitions **/
/** Logic Equations **/
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Old 11 May 2020, 14:16   #9
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http://www.devili.iki.fi/mirrors/hay.../rev9/u301.pld

is definitely CUPL. The other .PLD files most likely are also (didn't download them all to check though)
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Old 12 May 2020, 04:48   #10
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it's (Logical device's) CUPL.. that's the standard template (tmpl.pld) from the older dos / win3.1 variants..

they should generate fine under atmel's version.. just you might need to add Device _______; (G22V10.. G16V8s.. G22v10cplcc.. etc..) to make sure the fitter creates the right fuse map for the modern GAL part you're going to use.

Code:
Name       XXXXX;
Partno     XXXXX;
Date       XX/XX/XX;
Revision   XX;
Designer   XXXXX;
Company    XXXXX;
Assembly   XXXXX;
Location   XXXXX;

/******************************************************************/
/*                                                                */
/*                                                                */
/*                                                                */
/******************************************************************/
/*  Allowable Target Device Types:                                */
/******************************************************************/

/**  Inputs  **/

Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */

/**  Outputs  **/

Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */
Pin          =           ;      /*                                */

/** Declarations and Intermediate Variable Definitions **/






/**  Logic Equations  **/
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Old 12 May 2020, 11:09   #11
PurpleMelbourne
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Thank you for your combined Sherlock Holmes sleuthing gents (and/or ladies)

Quote:
Originally Posted by Khyron View Post
it's (Logical device's) CUPL.. they should generate fine under atmel's version.. just you might need to add Device _______; (G22V10.. G16V8s.. G22v10cplcc.. etc..) to make sure the fitter creates the right fuse map for the modern GAL part you're going to use.
Would it be better to small step each individual PAL to a GAL, or jump all the way to CPLD?


Quote:
Originally Posted by Wikipedia
Assisted Technology released CUPL (Compiler for Universal Programmable Logic) in September 1983.[6] The software was always referred to as CUPL and never the expanded acronym. It was the first commercial design tool that supported multiple PLD families. The initial release was for the IBM PC and MS-DOS, but it was written in the C programming language so it could be ported to additional platforms.[7] Assisted Technology was acquired by Personal CAD Systems (P-CAD) in July 1985. In 1986, PCAD's schematic capture package could be used as a front end for CUPL.[8] CUPL was later acquired by Logical Devices and is now owned by Altium Limited of Australia.[9] CUPL is currently available as an integrated development package for Microsoft Windows.[10]

Atmel releases for free WinCUPL (their own design software for all Atmel SPLDs and CPLDs)

So what would be the best choice for CPLD to get things happening quickly?
From a quick educational search, PAL are single use predecessors of GAL's which in turn are an early form of SPLD (S for simple), which is a small version of a CPLD (C for complex).

So how do we know the "capacity" of a given PAL from which we can determine the capacity of CPLD required to replace them? Obviously the pins that come and go from the complex of PLD's is a requirement. I'm guessing that 200 pins on the PALs will boil down to 84 or less pins in and out of the CPLD that contains a bunch of virtual PAL's inside it.

Atmel have a nice 5V 128 macrocell CPLD's with 84 io's that would be a simple 5 volt replacement for 5 volt PAL's.
https://www.microchip.com/wwwproducts/en/ATF1508AS


With Xilinx we can have double the capacity using 5 volt tollerant (but 3.3 v powered) XC95288XL. It comes in various numbers of pinouts, with more io's available with more pins. 208 pin is the highest for a conventional chip, and beyond that are the BGA (Ball Grid Array) chips which are different to solder and so require a different PCB.

So with the Atmel chip we have free software to use. What about with Xilinx?
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Old 12 May 2020, 11:50   #12
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If I were you, I'd check out the TF534 sources and the 68020/030TK sources to get an idea of what you are up against.

https://github.com/terriblefire/tf534 (Xilinx based)
https://gitlab.com/MHeinrichs/68EC020-TK (Xilinx based)
https://gitlab.com/MHeinrichs/68030tk (AMD Mach based)

I would think the best approach would be to try and replace each PAL in turn with a small CPLD (like XC9572) and verify at each step. Once all the logic is replaced you can condense it in to one larger CPLD.
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Old 14 May 2020, 17:02   #13
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I'm not entirely sure that you wouldn't be better off going through that CPLD code, drawing it as a logic diagram, working out the truth table and then starting from scratch.

Apart from anything there are features there that make no sense now.

I mean I understand why Commodore wanted to have B2000 as well as A2000 compatibility but for an open source design it would probably be easier just to have different code for the chip.
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Old 16 May 2020, 09:34   #14
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So do you think perhaps just make a new card which is "inspired by" A2630, Terrible Fire, and Matze's A500 030?

If it helps get more people able to make Amiga hardware, then perhaps eventually Amiga can make its way into schools as a well documented platform as a tool to learn engineering.
And we'd all dearly love to see more people supporting and using Amiga.

I guess a simple A2000 conversion of the card which Matze (from German A1k.org board) did would be easy enough and he gave his blessings on using his already working XC9500XL series CPLD code.

Or perhaps adapt it to be an open hardware Commodore Gemini dual 030 card?
https://www.amigawiki.org/doku.php?i...ion:cpu:gemini

The Spartan 3AN has NOR flash built in for its <100ms bootup time and I believe does not require a JTAG for its reprogramming, just copy the new bitstream over to it. So that would be very useful as a learning tool. It would be good to develop a cache on modeled from the Motorola documents on the subject.
With cheap cache from ebay you could have an L2 cache as fast as the internal L1 cache
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Old 16 May 2020, 12:22   #15
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Quote:
Originally Posted by PurpleMelbourne View Post
So do you think perhaps just make a new card which is "inspired by" A2630, Terrible Fire, and Matze's A500 030?

If it helps get more people able to make Amiga hardware, then perhaps eventually Amiga can make its way into schools as a well documented platform as a tool to learn engineering.
And we'd all dearly love to see more people supporting and using Amiga.

I guess a simple A2000 conversion of the card which Matze (from German A1k.org board) did would be easy enough and he gave his blessings on using his already working XC9500XL series CPLD code.
I think there is room for both, particularly as a learning exercise. Start off with the open A2630 and then take that with inspiration from the TF and Matze's 030 to make a new design.

In theory all an A2000/B2000 "CPU" slot is the same 86pin A500/A1000 expansion slot slightly optimised for CPU use rather than general expansion. It's 94% the same.

http://eab.abime.net/attachment.php?...3&d=1215262578

In summary I think this is the difference between a B2000 and others.

7M (pin 7) is missing from the A500 (and A2000)
28M (pin 9) is missing from the A500
COPCFG (Pin 11) is missing from the A500 (and A2000)
BG (CBG) (Pin 64) is slightly different in functionality from the A500 (and A2000)
BOSS (Pin 20) is missing from the A500 (and A2000)

What that means is that actually the fundamental differences between the A2000 and B2000 means that I was wrong earlier, that A2000/B2000 jumper is desirable as an expansion card designed for the A500 would work without issue in an A2000/A1000 and with a few changes would then work in the B2000. What might be nice is to see if the B2000 differences could be worked onto a card that could then be used in an A500 or A2000, essentially the ability for an expansion to be a co-processor rather than co-opt the entire system and require the original CPU to be removed to prevent DMA issues.

Quote:
Originally Posted by PurpleMelbourne View Post
Or perhaps adapt it to be an open hardware Commodore Gemini dual 030 card?
https://www.amigawiki.org/doku.php?i...ion:cpu:gemini
I really shouldn't read about what the engineers were trying to do with the Amiga. It just makes me sad mad.

Quote:
Originally Posted by PurpleMelbourne View Post
The Spartan 3AN has NOR flash built in for its <100ms bootup time and I believe does not require a JTAG for its reprogramming, just copy the new bitstream over to it. So that would be very useful as a learning tool. It would be good to develop a cache on modeled from the Motorola documents on the subject.
With cheap cache from ebay you could have an L2 cache as fast as the internal L1 cache
Well regardless of cache you want to put memory _on_ the "processor" board because it'll run at full speed rather than being limited by the main bus.

Equally if you have one of the full 32bit processors (and I presume you will) you can go above the 24bit 16Mb addressing boundary but that memory can't be auto-configured (anything below there should be left to auto-configure). A 32bit processor can of course address 4Gb of memory but I have *no* idea how that plays when you have the 24bit pre-existing registers. I know that there is the whole Zorro III register range which lets you get up to around 2Gb or so but again no idea when you are effectively playing with a Zorro I.
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Old 16 May 2020, 15:12   #16
PurpleMelbourne
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Quote:
Originally Posted by Fastdruid View Post
I think there is room for both, particularly as a learning exercise. Start off with the open A2630 and then take that with inspiration from the TF and Matze's 030 to make a new design.
That probably makes sense.
Matze already has the code to use SRAM in the bottom 16MB range. The only reason you would want to disable the fast CPU is for game compatibility, and so only a small amount of FAST RAM makes sense. It needs to be 16 bit accessable. So perhaps two 16 bit blocks of SRAM's accessable in series for 16 bit or parallel for 32 bit access.

Matze has also made available many CAD layouts for various Amiga components for Eagle. I imported these into DipTrace. I'll try and make it clean for others to import the files into either of those packages. But I don't know how KiCad works. I'd love some help.

I think the TF design has access to SDRAM. So it could handle the >24 bit memory range above 16MB. I'll have to try and find the designer to ask his blessing to build on his code.
Since the A2091 design is available, I'll consider it. But that involves the DMAC chip and reproducing it.

The design will be DipTrace. But that can export in Eagle format. And KiCad can handle Eagle format too.

Quote:
Originally Posted by Fastdruid View Post
In theory all an A2000/B2000 "CPU" slot is the same 86pin A500/A1000 expansion slot slightly optimised for CPU use rather than general expansion. It's 94% the same.


What that means is that actually the fundamental differences between the A2000 and B2000 means that I was wrong earlier, that A2000/B2000 jumper is desirable as an expansion card designed for the A500 would work without issue in an A2000/A1000 and with a few changes would then work in the B2000. What might be nice is to see if the B2000 differences could be worked onto a card that could then be used in an A500 or A2000, essentially the ability for an expansion to be a co-processor rather than co-opt the entire system and require the original CPU to be removed to prevent DMA issues.
If I remember correctly, almost all A2000's are actually B2000's, which is an improved version I guess with the changes you described.
Could you please explain again what you were saying about making a card to bridge the difference between the A2000 and B2000.


Quote:
Originally Posted by Fastdruid View Post
Equally if you have one of the full 32bit processors (and I presume you will) you can go above the 24bit 16Mb addressing boundary but that memory can't be auto-configured (anything below there should be left to auto-configure). A 32bit processor can of course address 4Gb of memory but I have *no* idea how that plays when you have the 24bit pre-existing registers. I know that there is the whole Zorro III register range which lets you get up to around 2Gb or so but again no idea when you are effectively playing with a Zorro I.
It'd be nice to have some decent speed (SRAM) accessable in 68000 mode, which I think is what the 2630 does. But additionally have a BIGRAM type expansion using regular 72 pin SIMMs, or maybe even 168pin SDRAM DIMMs.

So from what you are saying, autoconfig only works on the first 24 bit and beyond that the memory has to be installed as Zorro 3 expansion into specific memory locations?
IIRC the memory map has places for 64MB, 128MB and also 256MB, which works out fine for any of those amounts being available.

So I guess Refresh the PCB of the A2630 using currently available GAL's.
Next step will be see if the CUPL code can be ported to Verilog or VHDL and still used on those GAL's.

OK that is sounding like a long list. But I think others will be keen to lend a hand where I fall short
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Old 16 May 2020, 18:05   #17
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Quote:
Originally Posted by PurpleMelbourne View Post
I think the TF design has access to SDRAM. So it could handle the >24 bit memory range above 16MB. I'll have to try and find the designer to ask his blessing to build on his code.
Since the A2091 design is available, I'll consider it. But that involves the DMAC chip and reproducing it.
From what I remember about the TF designer it's under a licence that means you're free to modify but you *have* to make your changes equally public. Which isn't an issue for what you're doing.

Quote:
Originally Posted by PurpleMelbourne View Post
If I remember correctly, almost all A2000's are actually B2000's, which is an improved version I guess with the changes you described.
Could you please explain again what you were saying about making a card to bridge the difference between the A2000 and B2000.
Almost certainly so. The A2000 was the German designed version that was basically an A1000 with more Zorro. The B2000 was the Haynie designed version that took that plus the stuff from the A500 plus improvements.

Anyway, reading it through again this is not needed in an A500 and it's merely an A2000 issue (and they're rare enough to not be overly concerned about) as it's a DMA issue with and expansions that need to take over the bus.

It's all described here http://eab.abime.net/attachment.php?...3&d=1215262578 (page 8)

In super short, on the A500, A2000 the original CPU is kept halted by asserting /BR, waiting for a /BG and then holding /BGACK and /BR forever.

If otoh a Zorro II device attempts to do DMA by asserting BR (Bus Request) then it can't because /BR /BG and /BGACK are blocking ALL non-DMA devices.

On the A2000 owners would need to remove the original CPU. The B2000 deals with it by using Buster and having /CBR and /CBG.

If you have an A500 and don't want to remove the original *and* want to have additional devices *on* the card that do DMA you can just run the /BR,/BG,/BGACK on one of the PAL's to the original bus to hold the original 68k off the bus and let the device decide.

There is no buster chip (which is what handles things on the B2000) so generally more than one device isn't going to work _too_ well but that's kind of fine for an A500. The only reason for needing it would be if you wanted to do a full Zorro II expansion when you'd basically want a buster in there.

Quote:
Originally Posted by PurpleMelbourne View Post
So from what you are saying, autoconfig only works on the first 24 bit and beyond that the memory has to be installed as Zorro 3 expansion into specific memory locations?
I'm no expert I'm just reading the docs because this is interesting.

The issue is that on an A500/A2000/B2000 there is only 24-bit addressing on the main board. There _is_ no Zorro III address space on these because there is no Zorro III and with only 24bit addressing they can't address anything beyond 16Mb.

You need an A3000/A4000 for 32bit addressing (IIRC the A1200 also equally limited to 24bit).

This means that (and I'll quote Haynie here):

Quote:
Originally Posted by Dave Haynie
This directly connects to the 68000’s address bus, providing 16 megabytes of address space with 23 bits of
address for a 16 bit data bus. The 68000 is capable of driving only this much address space. Thus, any resources on
a coprocessor board must map somewhere into the 68000 memory space. The best thing to do with any such memory
is allow it to be autoconfigured by the 1.2 OS; this will place it somewhere in the 8 megabyte space starting at
$200000 (the A2000 doesn’t support autoconfiguration from the Coprocessor Slot, the B2000 does). Any resources
intended specifically for the coprocessor only can be located above the 68000’s 16 megabyte space if the coprocessor
hardware permits that extended addressing.
Quote:
Originally Posted by PurpleMelbourne View Post
IIRC the memory map has places for 64MB, 128MB and also 256MB, which works out fine for any of those amounts being available.
Note the note about the A2000 not doing autoconfigure but yes, Zorro III memory map would be be a good place to put extra memory as nothing on the (main) board could address it. If it's on an B2000 then it's the first autoconfigure device in the chain and so any additional memory is added nicely. If it's on an A2000 then the autoconfigure isn't passed on from the CPU board and so any additional memory on the Zorro II cards isn't autoconfigured properly.

If it's on an A500 then er not sure exactly but you're mostly not going to be adding Zorro II as well that isn't part of the card so it isn't that big a deal.
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Old 17 May 2020, 13:27   #18
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So what about this talk of dual CPU in B2000? It flew over my head. I don't see how it could work. Special hidden magic in the Buster chip?

What do you think about swapping the 68030 for the powerful 68360 comms chip. Its basically a super enhanced 68030 with dual core RISC bolted on the side for DMA transfers at 50MB/s on 25MHz chip. Also Ethernet and memory controller built in to the 240 pin monster.

Supposedly this chip can function merely as an enhanced 68030 with existing software. I'm curious to know if it works and how its speed compares to the other chips.

The chip can have its 030 labotomised and in place use an external 68040 or 060 CPU core in its place while continuing to use the DMA, memory controller and Ethernet of the 68360.

There is a PCI chip designed for it by Motorola which was taken over by IDT when Motorola abandoned the chip business.
IDT CA91L862A is designed for MC68360, MPC860 and MC68040.
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Old 17 May 2020, 13:41   #19
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Quote:
Originally Posted by PurpleMelbourne View Post
So what about this talk of dual CPU in B2000? It flew over my head. I don't see how it could work. Special hidden magic in the Buster chip?
It's in the docs. I find this fascinating as I'd never come across it before.

Essentially yes though, Buster handles Bus Request's for the Zorro II slots but also for the processor (on board) and co-processor (in the CPU expansion slot).

This means that on the B2000 both CPU's can request bus and work nicely together unlike other models where the expansion CPU takes over everything and the original CPU is left effectively shutdown. In the old days there would have been _no_ point doing this because the replacement CPU would have been massively better and of course the existing processor would have to run at board speed and hog the bus to do anything. I think it is largely theoretical rather than in any way practical, although it's related to how the PPC/68k works.

Now however you have a bunch of drop in options for the original 68k and you could have a matching replacement in the CPU slot, ie two identical fast processors which would each be buffered and with their own fast memory running at a multiple of bus speed. They could each be "doing their thing" and just requesting main board bus access when needed. I doubt there is anything to take advantage of it within the OS of course.

Gemini then does something entirely different with the newer buster (and that is special undocumented hidden magic).

Last edited by Fastdruid; 17 May 2020 at 13:48.
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Old 17 May 2020, 19:43   #20
Fastdruid
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Join Date: Apr 2020
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Posts: 144
Quote:
Originally Posted by PurpleMelbourne View Post
What do you think about swapping the 68030 for the powerful 68360 comms chip. Its basically a super enhanced 68030 with dual core RISC bolted on the side for DMA transfers at 50MB/s on 25MHz chip. Also Ethernet and memory controller built in to the 240 pin monster.
Can you get them still? A quick google suggest not and that the second hand ones are going for more than the 060. It would be an interesting experiment certainly.

Quote:
Originally Posted by PurpleMelbourne View Post
There is a PCI chip designed for it by Motorola which was taken over by IDT when Motorola abandoned the chip business.
IDT CA91L862A is designed for MC68360, MPC860 and MC68040.
From reading the datasheet the 68030 as well (with a bit of glue). It looks from a brief read (if I'm reading it correctly) as if it can act both as part of a PCI "card" (or PIC) as well as a backplane PCI controller which would be interesting.
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