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Old 25 April 2017, 11:41   #41
trixster
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Originally Posted by grelbfarlk View Post
So are we in agreement? Make a board that plugs into an 040 or 060 socket with the 040/060 plugging into it, with a fast PCI bus that goes out to a busboard with Zorro+PCI or the Mediator bridge slot. Someone ask Haynie if he can do that.
I believe that's the route the Atari guys went down with the CT60 and CTPCI.
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Old 25 April 2017, 20:53   #42
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Originally Posted by grelbfarlk View Post
To refresh anyone's memory this was the first post:

Dave Haynie has said he would have went with PCI if it was a standard around when Zorro-III was being created, he just gets to "make it right".
Has anything changed since August 2015? Making a Buster replacement for big box Amigas almost seems like a step backward, or at least side ways, from a replacement FPGA Amiga motherboard which Dave supported for the Amiga future. It would be different if the optimized buster logic could be used in an FPGA Amiga motherboard but it would likely be unnecessary as is with the Zorro slots disappearing. It would be great if Dave could be encouraged to get involved with one of the FPGA Amiga motherboard replacement developments as he is great for PR and motivation, he has insights and resources for some of the custom chip logic and his advice has been solid (C= didn't listen and they are bankrupt and Hyperion/A-Eon didn't listen and they are likely a tax deduction as well). The current FPGA Amiga developers could use more vision and planning for the future. Too bad they can't all work together for the next generation and mass produce very affordable hardware. Then again, it may be the politics and short sighted people he wants to avoid after experiencing the destruction of C=.
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Old 27 April 2017, 00:54   #43
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How do you think the Amiga hardware would look today if Commodore hadn't went bankrupt? How would the Amiga graphics system look? Would it be non standard and based on AGA/AAA or would it be more like SVGA? What about the bus system? And, last but least, what processor architecture could the Amiga have been using?

A: Well, it’s hard to say everything for sure. But I can tell you this. In the fall of 1991, with Sydnes basically cancelling every project, I decided to sit down and design the next system architecture, the thing that would hopefully replace the A3000 design (used in all A3000/A4000 machines). This was called “Acutiator”, and fully modularized the architecture, so that graphics, for example, could be separate from sound and basic I/O. This originally used a custom bus I designed, called the AMI Bus (Amiga Modular Interconnect).

But then a funny thing happened: PCI came out. PCI was designed to solve the very same problem, and by the time Intel kicked it out to the PCI SIG and they improved it, it was way better than the AMI bus at a bunch of things. And also, it was likely to be this huge standard. That’s a good thing....

See, there’s this misconception about C=/Amiga engineering and standards. We LOVED to use standards – any standard – as long as they did not suck. So you see all these proprietary buses and such around the Amiga, and figure, these guys hate standards. Not at all. We liked the good ones. PCI was a very good one, even then.

So, with all of that said, the next generation Amiga would have had a PCI bus. Also, probably, a PCI to Zorro III bridge. Graphics would have been on PCI. I had speced out PCI interface chips for AA and AAA subsystems, so the graphics could go on a card. Not at all cloning The PC; but the functionality is correct, to make these pieces modular if possible. I’ll let you say I’m copying the Apple ][ here is you like – after all, that’s what IBM did anyway.

There was a feature in Acutiator most systems simply don’t have: the TPU, or Transfer Processing Unit. Any time you had a bus to bus interface, you would (ideally) have a TPU there, in the chip that did that bus to bus interface. This was a very simple 32-bit microprocessor (I designed the architecture) which would transfer data, efficiently, from bus to bus. It would so largely because it understood, perfectly, both of the buses at issue. So, no imposed wait states if there were synchronization issues, speed mismatch, etc. You could write directly to memory/IO on the far side of that bus, but better still, just drop a transfer instruction into the queue for a particular TPU, and it would run the transfer for you, then signal when done. The goal: every bus in the system could be busy, all at once.

Anyway, that’s the kind of things I had in mind for the system. For graphics, Hombre, as mentioned, and that was also PCI – Dr. Hepler also saw the wisdom in PCI, even as I did independently. Beyond that, it’s questionable if Commodore would have remained in the graphics business. Most of the PC markers used to make their own graphics chips, too. Today, it’s nVidia, ATi, Matrox, and few others. Like Intel, Motorola, and National Semiconductor, you only need so many different CPUs around.
Source:
http://www.landley.net/history/mirro...re/haynie.html

Related to nothing, but I liked this interview with him.
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Old 31 August 2018, 22:57   #44
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this needs to be done a simple pop on board could be made to replace
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Old 01 September 2018, 00:10   #45
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Given bugger all happened in the three years since the thread was started, I won't hold my breath..
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Old 01 September 2018, 00:23   #46
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As an A3000 user, which back in the day could not find how and afford to upgrade it properly, this sounds very interesting!
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Old 14 May 2020, 16:38   #47
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Originally Posted by gulliver View Post
I would leave buster as it is, but add PCI to mix. It would open up a world of possibilities. Leave Zorro II/III as slow as it is and attempt to do something with PCI.
Awaken yee old thread!

In case you haven't looked for a while, you may not know there is now information on how the Fat Buster is designed.
https://www.amigawiki.org/lib/exe/fe...ts:buster2.pdf

An 040/060 version of Fat Buster could be made on a Programmable Logic chip, but it would also require accelerator card with ROMs changed to suit the new 040 Buster.

PCI bridge chips are on the market now for use with the 68040. Tundra took over the Motorola MPC105 PCI Bridge (designed for MPC850 PPC, and also 68040 bus) when Motorola exited the chip business.
Here's a snipped of Zorro3 detail from the link.
Quote:
Originally Posted by Dave Haynie in above link
The Buster chip performs two main functions in an Amiga system. It acts as a bus
protocol converter, translating 68030 cycles into Zorro II or Zorro III cycles, and Zorro II or
Zorro III cycles into 68030 cycles, as appropriate for a particular bus cycle. In addition, it acts as
the bus arbiter for bus requests originating on the Amiga local bus, or on the expansion bus
according to Zorro II or Zorro III protocols. The particular list of features is as follows:
• 68030 to Zorro II cycle conversion with proper synchronization. It supports cache
mapping of Zorro II space, "sloppy cycle" bus snooping, and Zorro II standard bus lock
conversion.
• 68030 to Zorro III cycle conversion, including 68030 burst to Zorro III multiple cycle
translation and quick interrupt cycle types.
• Zorro II and Zorro III to 68030 cycle conversion.
• PIC collision detection for Zorro II and Zorro III.
• Buffer control to support external data and address buffers necessary for Zorro II and
Zorro III bus operation, including a bridging buffer for funneling Zorro II DMA cycles to
either half of a 32-bit 68030 local bus.
• Time-multiplexed bus request for sharing with an alternate high-speed local bus master.
• One local bus 68030-protocol DMA channel.
• Five expansion bus Zorro II/Zorro III protocol DMA channels, with fair arbitration within
channel groups.
• Eight cycle Zorro III scheduling atom with LOCK* override and Zorro III grant timeout.
Documentation of the Cypress PCI chip stresses its mighty 128Kbit (16KB) dual port SRAM buffering.

So I was thinking for higher performance Buster than simply using a CPLD, an FPGA with Block RAM used for asynchronous buffering would be faster.

Each card given an 8KB Block RAM (what the very fast FPGA internal RAM is named) providing 256bit each 32 bit data burst to make up for the difference of speeds between each moving part. Each card could be run at a different speed, its own personal maximum, without slowing down the other cards.

Xilinx Spartan 3A-400 has 40KB and Spartan 6-9 has 64KB. The spartan 3 would be simpler to adapt, but the 6 is a bit faster and has a bit more Block Ram available. Either way, they could be reprogrammed to be upgraded as the design is improved. They are both designed for working with PCI so are more than capable for the job.

Has anyone begun work replacing Buster?
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Old 14 May 2020, 21:24   #48
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This thread is a textbook definition of scope creep. Proposal: create a buster replacement. Soon the thread goes all crazy and lands on an entire Amiga replacement project. This is why projects fail.

Replace Buster per-se with clearly defined goals or make a new Amiga.
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Old 14 May 2020, 23:53   #49
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Originally Posted by jasonsbeer View Post
This thread is a textbook definition of scope creep. Proposal: create a buster replacement. Soon the thread goes all crazy and lands on an entire Amiga replacement project. This is why projects fail.

Replace Buster per-se with clearly defined goals or make a new Amiga.
The OP is from nearly 5 years ago, lots of comments but going nowhere. While proposals are made there's nothing happening so I wouldn't clasify it as scope creap because there is no intended product, I would classify it as hypothetical what if.
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Old 15 May 2020, 12:47   #50
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5 years later and I'm less excited about a new buster, more accepting of PCI and a proponent of a BoXeR-esque 68k based design with a 68060 bus on the fast side of things and original custom chips on the slow side. :-)
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Old 15 May 2020, 15:36   #51
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I do believe that if HESE's A4000TX v1.1 is a success that he might try to integrate Prometheus which I believe the designer has made open source and E3B has improved. That would be pretty cool. But I think replacement AGA chips will become scarce very quickly. A full set is almost £200 today due to demand for A4000TX, AA3000+, reviveA1200 and other PCB projects (most of which will go in a box never to be assembled)
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Old 15 May 2020, 15:41   #52
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I do believe that if HESE's A4000TX v1.1 is a success that he might try to integrate Prometheus which I believe the designer has made open source and E3B has improved. That would be pretty cool. But I think replacement AGA chips will become scarce very quickly. A full set is almost £200 today due to demand for A4000TX, AA3000+, reviveA1200 and other PCB projects
I was just discussing these in tg today and basically things like the Warp4060 are most of the BoXeR dream.. They have the modern expansions on the fast side, then the whole motherboard is the slow side. :-)

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(most of which will go in a box never to be assembled)
The devil is in the build definitely. Takes a bit of seating muscles.
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Old 15 May 2020, 18:59   #53
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Custom ASIC prices are rapidly dropping and you could probably tape out a 350nm Amiga-on-a-chip (minus CPU, etc.) for a humanly-achievable amount of money. It would be pretty tiny considering that every custom chip in the A4000 was at 5000nm except Lisa which was at 1500nm.
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Old 15 May 2020, 20:46   #54
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Custom ASIC prices are rapidly dropping and you could probably tape out a 350nm Amiga-on-a-chip (minus CPU, etc.) for a humanly-achievable amount of money. It would be pretty tiny considering that every custom chip in the A4000 was at 5000nm except Lisa which was at 1500nm.
you would still need >10,000 customers to make it financially break even - this is a high mark for the Amiga retro market.

But before that you would need ether a complete system in FPGA* or a perfekt scan of all the chips including the CPU.

The available FPGA solutions are not really complete in terms of all the IO and are of course missing the Buster.
The Minimig core is considered as "unstable" by the maintainer of the MISTer port. The Vampire or Apollo core is not free ...

I really hope this will happen one day, but it is still a long way and would need all parties working together for a change to make it happen.

Last edited by Gorf; 15 May 2020 at 20:56.
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Old 15 May 2020, 20:53   #55
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"Matze" managed to successfully reverse engineered Gary and put it onto a Xilinx CPLD.

I wonder if a (5V?) CPLD might be a possible solution for Buster as well...

Click image for larger version

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https://amigalove.com/viewtopic.php?...28c64b6c#p7769
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Old 15 May 2020, 21:30   #56
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The MiSTer FPGA implementation takes some serious liberties as well because it just doesn't have to bother about a whole load of stuff that a real system would.
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Old 16 May 2020, 11:46   #57
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Any thoughts on if Minimig is complete enough to function as a replacement chipset?
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Old 16 May 2020, 12:33   #58
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Depends what you want to do with it.

There are a bunch of liberties taken because things like peripherals, memory etc are handled differently.

So it suffers the same issues as MiSTer in that regard.

Someone else pointed out that MiSTer doesn't properly replicate the full 32bit AGA memory bus but fakes it using a double speed 16bit memory access.

The issue being the difference between emulating something and making it work as well as it can. If you were going to want to make a custom ASIC you'd want to do significant re-work.
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