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Old 12 January 2020, 21:39   #61
Mathesar
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Quote:
Originally Posted by Iscord View Post
This circuit has too many problems... I fixed the obvious errors, but it still doesn't work.
I need to find a working one so I can compare the signals with oscilloscope.
Well, you did try
But there is indeed more than one problem in this accelerator.
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Old 24 January 2020, 13:54   #62
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Just an FYI - this was never once billed as 100% working and ready for use - it's a WIP project that i've put out there - the github exists for people to try it out, test, make changes etc - the whole point of this.

I've had barely any time to do anything electronics related in months, i'm happy to look into the issues here, when i have time.

What won't happen is for me to spring into action when people start slating me for putting this out there.

I already stated that it is NOT my schematic, that it's the livio plos schematic that i've put into KiCAD for all to have a go with.
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Old 05 February 2020, 18:38   #63
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Originally Posted by Mathesar View Post
You also need the driver which I modified from the original. I first have to contact the original author to have permission for that.
Hi, I was wondering if you found out anything on the status of this driver. I am also using a modified version for my own A2000 IDE interface. It would be cool if we could redistribute an open source version with improvements, don't you agree? (bootable ROM-resident version would be especially nice)

The original driver has some delay loops that can run too fast on my '030. The sector read/write code also is not ideal for '030 because the unrolled loop thrashes the instruction cache. I got better performance (2.5MB/s) with a small loop and 32-bit MOVEs.

When /IOR or /IOW command lines are delayed a little bit beyond /AS going low, as well as returning high immediately when /AS goes high, timing seems to be agreeable enough for back-to-back reads. See this scope capture: http://www.hyakushiki.net/misc/ide755.png

Top signal is /CS0 (A12), bottom is /IOR
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Old 06 February 2020, 22:26   #64
Mathesar
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Quote:
Originally Posted by DamageX View Post
Hi, I was wondering if you found out anything on the status of this driver. I am also using a modified version for my own A2000 IDE interface. It would be cool if we could redistribute an open source version with improvements, don't you agree? (bootable ROM-resident version would be especially nice)

The original driver has some delay loops that can run too fast on my '030. The sector read/write code also is not ideal for '030 because the unrolled loop thrashes the instruction cache. I got better performance (2.5MB/s) with a small loop and 32-bit MOVEs.

When /IOR or /IOW command lines are delayed a little bit beyond /AS going low, as well as returning high immediately when /AS goes high, timing seems to be agreeable enough for back-to-back reads. See this scope capture: http://www.hyakushiki.net/misc/ide755.png
Top signal is /CS0 (A12), bottom is /IOR
Hi, and welcome to EAB!
I don't know the license status of this driver. However, i think it is ok to tinker with it. So you have been playing with it as well? I also had to adjust some delays as in my case they were way too long causing hdtoolbox to freeze when scanning the slave drive. I also added some error handling in the driver as that was either non existant or broken. The driver can now reliably detect and/or ignore a slave drive.
I agree about the ior/iow timing. In my version of the hardware I adjusted the timing as you described and indeed 32bit moves work well. See this diagram from my notebook:
Click image for larger version

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Did you use the original hardware or did you also modify it?
Like you I got most performance using a small loop as well but only on an 68010. On the 68000 an unrolled loop worked best. I never tested and 68030.
It would indeed be great if we could make this driver romable and bootable.
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Old 07 February 2020, 17:44   #65
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I was confused about how to set it up with hdtoolbox. Currently I am using a mountlist with FAT95 to mount a disk originally formatted on my PC.

I am going through trial and error with the hardware. My test board was designed with a few TTL chips and it had a few address ranges that I could set it to. On the A2000 Zorro slot it was not possible to run $DA0000. I could run it at $80-$900000 but only with the data cache turned off. I assembled a second board with just a PLD hooked up to map it at $EF0000, and fine tuned the timing a bit with the PLD. But like the original A500IDE project, there is no buffering of the data bus, so if I plug in additional Zorro cards then the signal becomes too weak and communication fails.

I'm considering a board redesign with buffering, ROM socket, and autoconfig controlled by a PLD.

Although for A500s without Zorro slots it might be good to replace scsi.device inside the kickstart ROM to make it bootable instead. I'm not sure which is easier.
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Old 08 February 2020, 01:48   #66
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Cute board, I like its simplicity and modest aims. Did this used to work in 1992 and now it's a problem of layout and component selection?
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Old 09 February 2020, 14:57   #67
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Cute board, I like its simplicity and modest aims. Did this used to work in 1992 and now it's a problem of layout and component selection?
Tempting isn't it?????
I think this kinda worked in 1992... if you used the motherboard 14MHz clock instead of the local doubled clock.
Combine this with Mika's A500ide and you have a nice accelerator/hd combo that anyone can build. No programming tools required!
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Old 10 February 2020, 12:01   #68
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Originally Posted by Mathesar View Post
Tempting isn't it?????
I think this kinda worked in 1992... if you used the motherboard 14MHz clock instead of the local doubled clock.
Combine this with Mika's A500ide and you have a nice accelerator/hd combo that anyone can build. No programming tools required!
Yes, add this to your IDE board. I ebayed a couple MC68HC000FNs

Did Iscord try your idea of changing the caps? Seems like a solvable problem. There is an error in the schematic of connecting CDAC to the R-C delay, but I guess Iscord already fixed that. Using CDAC was meant to be a jumperable option INSTEAD of the R-C delay, is my understanding.

How does this work with fastRAM, it just accesses it at 14 MHz and assumes it'll keep up?
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Old 10 February 2020, 12:12   #69
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Wow, check out that "clock" circuit. Don't waste your time with this board guys, it's a terrible design.
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Old 12 February 2020, 12:35   #70
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Wow, check out that "clock" circuit. Don't waste your time with this board guys, it's a terrible design.
Nothing that can't be fixed. I have an idea for a better (and still simple!) clock doubler that does work and uses somewhat period-correct parts
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Old 12 February 2020, 13:16   #71
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Maybe put a PLL on there or is it too easy?

https://www.diodes.com/assets/Datasheets/PT7C4511.pdf
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Old 12 February 2020, 13:51   #72
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Originally Posted by jbilander View Post
Maybe put a PLL on there or is it too easy?

https://www.diodes.com/assets/Datasheets/PT7C4511.pdf
Naah, too easy But probably even better than this:
https://www.google.com/url?sa=t&rct=...dpoEG39CRzHNY0
This is an old school (period correct) PLL in a DIP package that can run up to 16Mhz or so. But, if you let it run at just 7MHz and use the XOR-type phasedetector, the output of the phasedetector will be a nicely doubled 14MHz clock.
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Old 13 February 2020, 03:20   #73
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Originally Posted by Mathesar View Post
Naah, too easy But probably even better than this:
https://www.google.com/url?sa=t&rct=...dpoEG39CRzHNY0
This is an old school (period correct) PLL in a DIP package that can run up to 16Mhz or so. But, if you let it run at just 7MHz and use the XOR-type phasedetector, the output of the phasedetector will be a nicely doubled 14MHz clock.
If you are going to tinker with this, take care with the Kicad schematic. I think VMA (pin 19 of old 68000 socket) is driven wrongly. It should come out of a 74LS157 mux. IMO I would dump the 157s altogether and just put 5 jumpers, low-tech and smaller

Does your clock idea cater for 21MHz for later?
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Old 13 February 2020, 20:59   #74
Mathesar
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Originally Posted by PeteAU View Post
If you are going to tinker with this, take care with the Kicad schematic. I think VMA (pin 19 of old 68000 socket) is driven wrongly. It should come out of a 74LS157 mux. IMO I would dump the 157s altogether and just put 5 jumpers, low-tech and smaller

Does your clock idea cater for 21MHz for later?
To go beyond 14Mhz would probably be better done by a proper, modern pll.
But for a simple, old school doubler the 4046 would do the job.
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Old 15 February 2020, 14:20   #75
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I have gone through the thread and from what I understand two cards are under discussion in this; one presented in the first post and another presented in post 25. The one posted at post 25 can take same cpu format as original on the Amiga. Both cards run at 14MHz, i.e. - CPU must be able to handle this much, i.e. - cannot use the original CPU.

Is the above all correct?

If I have no interest in IDE and FastRAM as I already have a card for that then is the design presented in post 25 usable? Or this too is work in progress?

Last edited by Sim085; 17 February 2020 at 12:28.
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