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Old 15 June 2017, 14:29   #1
Nightfox
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Floppy disk MC68000 series tutorial series

Hello everyone,

I have begun writing a series teaching 68k assembly from the basics and will eventually move onto Amiga specific coding.

If you're a beginner then feel free to check out part 1 here and if you want to get updated to more parts feel free to follow me (you'll need a free account to follow me). And while you're there, you can all make money by simply making posts or even commenting on other people's posts. Every single up-vote you receive from a person gets you real money, even if its just a comment you made on someone else's post. This site is going to be bigger than Reddit! It's really exciting actually. You guys can also feel free to share your wisdom on there too if you want.

https://steemit.com/programming/@sac...part-1-revised

Last edited by Nightfox; 08 July 2017 at 01:53. Reason: Linked to revised article
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Old 16 June 2017, 12:04   #2
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That was interesting indeed. Cheers.
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Old 16 June 2017, 15:06   #3
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That was interesting indeed. Cheers.

I get an "Sorry, this page does not exist"?
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Old 16 June 2017, 16:52   #4
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Thanks! I'm very interested but the link gives an error.
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Old 17 June 2017, 11:17   #5
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Hi Nightfox...

I posted here but not on that new forum..

I am in no way a coder, but I know enough about chips, in your first article, you are explaining about the instructions (Mips, Instructions per second) versus Mhz (Frequency of operation).

Quote:
For example, the stock M68000 CPU runs at 7Mhz, that is, 7 million instructions per second
In your example, you put 1Mhz at 1Mips, where this being a 68000 example (or any 68000 series Processor), you cannot directly co-relate MIPS with the frequency.

The 68000/8 (8Mhz) will in NO WAY IN HELL run at 8 MIPS, because you are limited by how many instructions you can execute, in any one given clock cycle. To say that the CPU is efficient to execute one instruction per cycle, is at a push optimistic. the 68000, you might be VERY LUCKY, if your code is optimized, to get away with an instruction every 4 cycles.

the official documentation puts the 68000 at around 0.175 instructions per cycle, which gives you roughly 1.3 Mips at 8Mhz.

Moving up to the 68030, which is an optimized 68020 core, you are pushing maybe 9Mips at 25mhz. (Official docs put it at about 0.36 instructions per cycle, notice its more efficient than the 68000).

But then, this is where things get really bloody funky, the 68060, is rated at 1.33 instructions per cycle, more than 1:1, at about 110 Mips at 75Mhz.

Fast forward from the 80's and 90's, CPU's are *VERY* efficient, with the I7 rated at 106:1 (10.6 Instructions per cycle) so.... 317,000 Mips at 3Ghz.

Its all about the efficiency of instructions per cycle (Where on the cycle, and how many), and in the 68000 series, no where near 1:1.

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Accelerator boards are available to provide better models of the CPUs such as 68030, 68040 and 60860. What happened to the 68050? Apparently Motorola forgot how to count.
They didnt forget to count the 68050, it was an internal project, with faster clocks and higher heat dissipation than the 68040, but the 68000 series was advancing fast enough to warrant a series skip direct to the 68060.

The 68070 was never produced, but was licensed by, and used by Philips, in its CD/I, and because it was produced by Philips, it was never an official Motorola line.

Motorola always released in Evens (000, 020, 040, 060), with odds (010, 030, 050) being revisions of the parent core. 68000 - 68010 (I had one, at 12Mhz with the only beneficial instruction used by WHDLOAD to execute the QUIT command back to DOS), 68020 - 68030, 68030 was MORE popular, it was majorly used in MAC's, as well as a lot of Cisco routers at the time, which is why, if you look for a 68030, try to get a hold of an Apple Mac (with the built in monitor), or a Cisco 2500 Series.

Last edited by whiteb; 17 June 2017 at 11:50.
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Old 29 June 2017, 23:26   #6
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Thanks for the info whiteb. It seems the link is indeed working.. it works for me. Part 2 is up and available here: https://steemit.com/programming/@sac...utorial-part-2
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Old 30 June 2017, 02:40   #7
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Originally Posted by Nightfox View Post
Thanks for the info whiteb. It seems the link is indeed working.. it works for me. Part 2 is up and available here: https://steemit.com/programming/@sac...utorial-part-2
Awesome, thats good that you linked Easy68k.., didnt know about that.., thats cool.

it also sort of backs up my argument about not getting 1:1 instruction per cycle on an MC68000.

2 lines, 16 cycles.. so an average of 8 cycles per instruction. (ouch).

So we jump to the final example, of 7 instructions, at 56 cycles. See how we are not getting one instruction per cycle ?, so, yeah, no way in hell are you gonna get 1mips at 1Mhz out of an MC68000. again, an instruction per 8 cycles.

also, move.b #5,d0 (moving a single byte in to d0) you are better off moveq #5,d0. 4 cycles faster. the full 7 instructions executes in 52 cycles, not 56. (See.............. You taught me something)

Sorry for being picky

Last edited by whiteb; 30 June 2017 at 04:08.
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Old 30 June 2017, 03:49   #8
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Awesome, thats good that you linked Easy68k.., didnt know about that.., thats cool.

it also sort of backs up my argument about not getting 1:1 instruction per cycle on an MC68000.

2 lines, 16 cycles.. so an average of 8 cycles per instruction. (ouch).

So we jump to the final example, of 7 instructions, at 56 cycles. See how we are not getting one instruction per cycle ?, so, yeah, no way in hell are you gonna get 1mips at 1Mhz out of an MC68000. again, an instruction per 8 cycles.
The 68000 design was slow but had a nice ISA with many wide registers. The 68020 and 68030 could not even peak at 1 instruction/cycle. It wasn't until the 68040 that a peak of 1 instruction/cycle was achieved. It wasn't until the superscalar 68060 that an average of 1 instruction/cycle was surpassed (peak of ~3 instructions/cycle).
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Old 30 June 2017, 11:08   #9
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This is how I always understood 68k clock timings (maybe I'm wrong but it made sense to me when I was learing about this stuff and it stick in my memory)...
You could say that it takes 1 minute to complete something, but you could also say it takes 60 seconds. It's the same amout of time but the numbers are very different, and the latter is more future proof (if your current cpu takes 1 cycle, does you nextgen cpu take 0.3333 cycles? sure it does, but all these timings written as fractions is annoying at the least).
Now about 68k... Its internal clock is 2x external, right? So basically you multiply all cycles by 2. And since it has no pipelining, it does fetch/execute/fetch/execute/... So you could say fetch is (2x)1+ cycles, execute is another (2x)1+ cycles. So there you have your super simple instruction, taking 1 cycle on some other cpu, taking 4 'cycles' on 68k.
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Old 30 June 2017, 17:00   #10
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You could say that it takes 1 minute to complete something, but you could also say it takes 60 seconds. It's the same amout of time but the numbers are very different, and the latter is more future proof (if your current cpu takes 1 cycle, does you nextgen cpu take 0.3333 cycles? sure it does, but all these timings written as fractions is annoying at the least).
Usually a person talks about the old CPUs and uses cycles/instruction or the new CPUs and uses instructions/cycle. Amiga 68k CPUs just so happen to be in the transition where talking about both together is common so there will be some small fractions as there is a huge performance gap between the 68000 and 68060.

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Originally Posted by a/b View Post
Now about 68k... Its internal clock is 2x external, right? So basically you multiply all cycles by 2. And since it has no pipelining, it does fetch/execute/fetch/execute/... So you could say fetch is (2x)1+ cycles, execute is another (2x)1+ cycles. So there you have your super simple instruction, taking 1 cycle on some other cpu, taking 4 'cycles' on 68k.
I don't know the internals of the 68000 well. I have heard that part of the reason it is so slow is the micro-coding which allowed it to be created faster. It is doing 16 and 32 bit operations which were slower at that time than 8 bit operations but could do twice or quadruple the work when needed. Usually only simple register only instructions are 4 cycles on the 68000. Most basic CISC style ALU instructions are 6-12 cycles. The lack of 68000 pipelining and parallelism make it very easy to look up the instruction timings.
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Old 01 July 2017, 03:14   #11
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I will be sure to mention the point in part 3 in basic form. I don't want to overwhelm the learner with technical information
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Old 06 July 2017, 22:23   #12
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Part 3 is now up

https://steemit.com/programming/@sac...utorial-part-3
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Old 06 July 2017, 22:37   #13
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Just noticed this tutorial. Very well made, thanks
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Old 06 July 2017, 22:49   #14
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Just noticed this tutorial. Very well made, thanks
ingen Śrsak
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Old 07 July 2017, 16:23   #15
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Hello Nightfox,

just wanted to point out an error in Part 1 / Hexadecimal section where you convert $A4F5 to decimal and you get 1013 as a result (5 + 240 + 128 + 640 = 1013) - should be 42229 (1x5 + 16x15 + 256x4 + 4096x10).

Other than that, thumbs up for the series, nicely done and very welcome to everyone that wants to start learning asm
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Old 07 July 2017, 16:40   #16
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Hello Nightfox,

just wanted to point out an error in Part 1 / Hexadecimal section where you convert $A4F5 to decimal and you get 1013 as a result (5 + 240 + 128 + 640 = 1013) - should be 42229 (1x5 + 16x15 + 256x4 + 4096x10).

Other than that, thumbs up for the series, nicely done and very welcome to everyone that wants to start learning asm
Thanks. I appreciate any corrections from the Amiga community!
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Old 08 July 2017, 00:27   #17
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I have put in a revised version here. https://steemit.com/programming/@sac...part-1-revised

Unfortunately it won't let me edit the original post... but I have posted the revised version and will link to that one from now on. Thank you everyone for correcting my stupidity.
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Old 08 July 2017, 00:58   #18
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Thank you for taking the time to do this!
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Old 08 July 2017, 01:49   #19
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Thank you for taking the time to do this!
You are most welcome

After this series I will move onto actual Amiga specific coding
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