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Old 08 February 2019, 08:56   #1
kaffer
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Killing caches: fool-proof method?

Hi,

Does anyone have a nice blob of code for disabling caches across all 680x0? Let's assume this is just before or after taking over the system, ExecBase still available. I'm aware there's a little dance of poking control registers that may not all exist so need to be tested for, or the resulting exceptions handled.

Alternatively (or as well): would CacheControl(bits=0,mask=-1) be suitable system-friendly approach? I haven't actually yet found an example of someone calling this to disable all caches, but I guess I haven't foraged *that* hard.

Cheers!
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Old 08 February 2019, 11:35   #2
hooverphonique
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If you have LVOCacheControl available, it should be fine. Beware that you need Exec V37+ for it to be present.
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Old 08 February 2019, 12:26   #3
ross
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000~060, all KS

Code:
start
	move.w	#$4000,$dff09a
	movea.l	$4.w,a6
	lea	super(pc),a5
	jsr	_LVOSupervisor(a6)
 	move.w	#$c000,$dff09a
	rts

super
	moveq	#0,d0
	lea	trap(pc),a5
	lea	$10.w,a1
	lea	$2c.w,a2
	movea.l	(a1),a3
	movea.l	(a2),a4
	move.l	a5,(a1)
	move.l	a5,(a2)
	dc.l	$4e7b0801	;movec d0,vbr
	dc.l	$f4784e71	;cpusha dc
	dc.l	$4e7b0002	;movec d0,cacr
	dc.l	$4e7b0808	;movec d0,pcr
	move.l	a3,(a1)
	move.l	a4,(a2)
	rte
trap	addq.l	#4,2(sp)
	rte
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Old 08 February 2019, 13:50   #4
kaffer
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Quote:
Originally Posted by ross View Post
000~060, all KS
That's the blob I need. Awesome, thanks!
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Old 08 February 2019, 22:08   #5
jotd
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I remember CPUSHA BC (branch cache? 68060?)
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Old 08 February 2019, 22:44   #6
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ross's example code sets VBR to 0 in the supervisor routine but doesn't restore it afterwards. May not be a problem if you're killing the system/OS anyway though.
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Old 08 February 2019, 22:53   #7
ross
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Quote:
Originally Posted by jotd View Post
I remember CPUSHA BC (branch cache? 68060?)
Hi jotd, see this message http://eab.abime.net/showpost.php?p=...5&postcount=15
CPUSHA pushes and possibly invalidates selected cache lines (IC=instruction, DC=data, BC=both).
BC works, but if you disable all caches (CACR=0) then a DC suffice.
For the 060 i've disabled also the Superscalar Dispatch (ESS bit in PCR register).

Last edited by ross; 08 February 2019 at 23:05. Reason: typo, written BC insted of DC
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Old 08 February 2019, 23:00   #8
ross
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Quote:
Originally Posted by mark_k View Post
ross's example code sets VBR to 0 in the supervisor routine but doesn't restore it afterwards. May not be a problem if you're killing the system/OS anyway though.
Yes, i've used it in a non-return ambient.
You can simply add:

Code:
	move.l	a5,(a2)
	...
	moveq	#0,d1
	movec	vbr,d1
	...
	dc.l	$4e7b0801	;movec d0,vbr
Also the cache and special registers can be saved in the same way.

EDIT: well, the moveq #0,d1 actually only serves if you plan to use the previous base and you are on a 000
not much if the next instruction is movec d0,vbr, so one of the two can be removed

Last edited by ross; 08 February 2019 at 23:26.
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Old 08 February 2019, 23:25   #9
jotd
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I like the way your code does NOT test CPU family explicitly. Nice.
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Old 09 February 2019, 10:54   #10
kaffer
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Quote:
Originally Posted by mark_k View Post
ross's example code sets VBR to 0 in the supervisor routine but doesn't restore it afterwards. May not be a problem if you're killing the system/OS anyway though.
Is it a problem even if you don't kill the system? Obviously it's a bit rude, but I assume the vectors at 0x0 are actually the originals, never change after boot, and the ones pointed at by the VBR are copies?

Zeroing VBR in this routine is quite nice if you're eventually killing the system: in some cases whatever you end up jumping into might well not consider non-zero VBR itself.

Secondly I wondered whether touching INTENA is necessary -- is it just because touching exception vectors is frowned on? I suppose it might stop AV or debug software going nuts.
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