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Old 13 August 2020, 02:55   #341
NovaCoder
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Hi Kipper,

Would it be possible to feed some of the TG68k core improvements made to the MiSTer FPGA project?

More speed is always appreciated


That Atari "suska" project mentioned above also sounds promising...
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Old 13 August 2020, 14:28   #342
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Hi Kipper,

Would it be possible to feed some of the TG68k core improvements made to the MiSTer FPGA project?

More speed is always appreciated


That Atari "suska" project mentioned above also sounds promising...
Hi,

Mike has been looking at the suska to see what state it is in, so far the TG68 core has not been changed, the latest sysinfo score is a result of th glue logic. He has said that any changes to the TG68 core will be published so Mister could benefit also
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Old 28 August 2020, 20:15   #343
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May I suggest testing it with the A1200+ by Jeroen Vandezande. It has no CPU, so you are forced to use an accelerator like yours
https://bitbucket.org/jvandezande/am...00/src/master/
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Old 30 August 2020, 16:40   #344
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May I suggest testing it with the A1200+ by Jeroen Vandezande. It has no CPU, so you are forced to use an accelerator like yours
https://bitbucket.org/jvandezande/am...00/src/master/

But does he has boards made?
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Old 30 August 2020, 19:42   #345
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But does he has boards made?
No, the board is open source hardware, so you can order the PCB yourself
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Old 01 September 2020, 22:47   #346
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Making one now for A1200 expansion slot is way different from what Mike was trying up to this point. 68020 interface is slightly different from 68000, both timings, data bus width and cpu signals. So it requires also different FPGA I/O mappings and whole "external interface" logic as well. I believe it's best to focus on finishing one design and making it flawless before diving into something different when the first task isn't even finished yet.
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Old 05 September 2020, 10:54   #347
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No, the board is open source hardware, so you can order the PCB yourself
Would be cool, if somebody would make a completely "passive" a1200 board, so other can concentrate on the turbo/fpga cards ...
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Old 11 September 2020, 10:28   #348
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Reading the latest blog entry, this board is look very tasty indeed. If and when these are released out in to the wild, I sense I'll have a "shut up and take my money" moment
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Old 17 September 2020, 13:36   #349
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@alexh: I will give some details on the cache architecture once released. I'm actually trying some different approaches at the moment to see if I can get any more performance out, particularly in overcoming DRAM latency.

@rabidgerry: The internal Gayle emulation would conflict with a motherboard Gayle (I actually think it will just override it altogether, so on a 600 the accelerator's SD card will probably work and the PCMCIA and on-board IDE will not). There will be some way to inhibit the emulated Gayle though, either through a flash configuration option or with a jumper.

Mike

You could always move the registers to a non conflicting area and include AROS scsi.device with the new offset so both devices (onboard IDE and your IDE) coexist happily.


Disabling PCMCIA on A600/A1200 is a very bad idea, it's quite comfortable to interchange data without drilling holes. Moreover it would be cool if your board could include a rom module to boot from PCMCIA. PCMCIA Network cards are usually faster than spi thingies too.


I would prefer a simpler and cheaper "adaptor" board to connect altera developer boards like DE-10, nano or even chinese aliexpress fpgas. That way it will be less work to build in quantity and you'll be able to produce lots. You won't depend much on fpga cost, you won't have to solder many pins, you'll have less production problems.


Keep in mind that if target price is around 200€ you will just sell a few because vampires offer a better fpga core, RTG and better support. In contrast if you just sold the "carrier" boad for let's say 69€ for example and allow connecting an Altera DE-10 for the same target price you planned the user will have a much much more powerful FPGA with even onboard ARM and your investment/risk will be much lower. Just:
-a few level shifters/buffers
-a 10x10 4 layer pcb.
-a few pin headers
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Old 17 September 2020, 16:32   #350
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connect altera developer boards like DE-10, nano or even chinese aliexpress fpgas
Altera dev boards aren't that cheap and that's one reason behind this project, to built fairly inexpensive turbo. And when it comes to chinese fpga dev board there's basically only one pretty decent company with boards worth a look and that's qmtech. QMTECH Altera products have only Cyclone IV, Cyclone V and Cyclone 10 with average number of LEs (16-40k iirC) and small SDRAM memory. Yes, those are quite cheap but also poor. When it comes to QMTECH Xilinx boards that's whole different story. You have 35k LC Artix 7 or even 100k LC Artix 7, you have ~28k LC with ZynQ (and 2 arm cortex a9 cores, yes, like ZZ9000) and what's the best, you have pretty big (256MB) DDR3 mem on-board. But porting to Xilinx would eat a lot of time I guess. Oh, btw Xilinx boards seems to be even cheaper
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Old 17 September 2020, 17:22   #351
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Altera dev boards aren't that cheap and that's one reason behind this project, to built fairly inexpensive turbo. And when it comes to chinese fpga dev board there's basically only one pretty decent company with boards worth a look and that's qmtech. QMTECH Altera products have only Cyclone IV, Cyclone V and Cyclone 10 with average number of LEs (16-40k iirC) and small SDRAM memory. Yes, those are quite cheap but also poor. When it comes to QMTECH Xilinx boards that's whole different story. You have 35k LC Artix 7 or even 100k LC Artix 7, you have ~28k LC with ZynQ (and 2 arm cortex a9 cores, yes, like ZZ9000) and what's the best, you have pretty big (256MB) DDR3 mem on-board. But porting to Xilinx would eat a lot of time I guess. Oh, btw Xilinx boards seems to be even cheaper
Yes, the QMTECH Cyclone V board looks like great bang for your buck:
https://www.aliexpress.com/item/1000...358a3dc0pKStfE

They even have a GitHub repository with all the information you need:
https://github.com/ChinaQMTECH/QM_CYCLONE_V

Someone also built an awesome Minimig IO board to be used with a QMTECH board:
https://github.com/ranzbak/qmtech_minimig

Last edited by CD32Freak; 17 September 2020 at 17:31.
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Old 17 September 2020, 17:51   #352
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Check the RAM. That board has SDRAM while the Xilinx has DDR3 mostly.
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Old 17 September 2020, 17:55   #353
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@CD32Freak - that's not only the one thing... unamiga is basically QMTECH board soldered on top of PCB with interfaces, audio and video. I believe that's the best option for fairly cheap accelerator but 32MB of SDRAM is limiting factor.
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Old 17 September 2020, 18:19   #354
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@Crumb - There is always room for more accelerators in the Amiga market, so if you have strong opinions about how it should be done you should go ahead and make it. After all, it's just a few level shifters and some pin headers.
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Old 17 September 2020, 18:32   #355
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After all, it's just a few level shifters and some pin headers
If only that was true I'm afraid it's more than that. But hey, majsta already proved it can be done. He had to design whole board and solder all components by himself. We don't. And we have better, faster, cheaper chips to our disposal. Don't worry, there'll be enough of affordable FPGA designs in no time. Maybe not absolutely stable and not with lots of goodies initially but once refined design will surface and go FOSS ... well, let's just say I'm rather optimistic about what future holds.
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Old 18 September 2020, 13:51   #356
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@Crumb - There is always room for more accelerators in the Amiga market, so if you have strong opinions about how it should be done you should go ahead and make it. After all, it's just a few level shifters and some pin headers.

If you read carefully you'll notice I never said creating an accelerator is a "simple" job. But It seems you think that designing and routing multi layer complex boards with hundreds of traces and pins and/or soldering bga chips is a piece of cake (compared to designing a carrier board). You could design your own accelerator if it's so easy.


1st hint: What mkstr has already done is exactly what I have described: a carrier board where you connect a cheap developer board like the DE0-Nano. What I'm saying is that IMHO it would be better to release just a "carrier" board, less investment risk, easier&cheaper&faster production. And yes: the materials are easier to buy and cheaper (voltage/signal level conversion) because the complex and expensive parts are included in the developer board. Developer boards also have more stable prices while fpgas sold as components are subject to more price fluctuation.



2nd hint: What Unamiga guys created was a simple ports addon board to use cheap developer boards. They could have created a new pcb but it's more risky and you can't focus on improving fpga core, instead you have to take much more care of other issues.

3rd hint: both mnt va2000 proto and zz9000 use fpga developer boards

4th hint: TG68K core was born on an Altera DE board connected directly to an A500 68000 socket with lots of cables. Now developer boards are quite small.

5th hint: Apollo core development was partly done on a "phoenix" carrier board connected to an A500 (A solution that could have been quite satisfactory for me)


FYI The fpga developer board used for MISTer is way more powerful than Vampire 4sa one, and way cheaper too. It would have been cheaper to release V4sa as an addon board, it would have been released earlier and if a better fpga comes out it's easier to adapt.

Last edited by Crumb; 18 September 2020 at 14:10.
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Old 18 September 2020, 15:12   #357
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FYI The fpga developer board used for MISTer is way more powerful than Vampire 4sa one, and way cheaper too. It would have been cheaper to release V4sa as an addon board, it would have been released earlier and if a better fpga comes out it's easier to adapt.
It seems the reason they build everything on one single board was to avoid making their wife/girlfriend angry for having a big computer on the desk
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Old 18 September 2020, 16:10   #358
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FYI The fpga developer board used for MISTer is way more powerful than Vampire 4sa one
Depends on what you claim is "powerful" - TG68 takes less LE than AC68080 and is less powerful and as far as I know MiSTer implementation of Amiga chipset doesn't offer too much improvement. AC68080 uses less LE than Cyclone V E A5 has (77k) so switching to Cyclone V SE A6 doesn't automatically make it better. What SE has is... dual core ARM Cortex A9 800MHz. That's pretty powerful but you can't make a good use of it under AmigaOS 3.x without writing proper software. In fact dual core A9 smashes and thrashes whatever Apollo team might come up with but it doesn't change the fact it's not immediately usable by AmigaOS. Hence Apollo still managed to pack fastest 68k implementation + fpu + rtg + improved AGA in just 77k LE. There's plenty of things more LE might help but fancy ARM core helps even better in most (like mpeg2, jpeg, mp3 etc.)

And true - having removable FPGA board (e.g. using pressfit connectors) allows to have different cores for different usages. If you just want cheap 030-like turbo with ram and storage - fairly cheap devel board and less powerful softcore. If you want to upgrade to 060-like and rtg - just switch board to bigger fpga and flash better core. Also cuts a lot of hw development cost. But... also makes PITA when it comes in maintaining cores for each and every pin compatible and usable devel board.
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Old 18 September 2020, 16:43   #359
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TG68.C supports caches but isn't pipelined. The SUSKA 68030 is pipelined with no caches. Maybe someone can figure out how to add caches and a barrel shifter to SUSKA to get up to 040 level performance. It'll need a second pipeline for 060 performance.
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Old 18 September 2020, 19:25   #360
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Someone also built an awesome Minimig IO board to be used with a QMTECH board:
https://github.com/ranzbak/qmtech_minimig

That seems to be pretty cool. Did you find any pictures of this board?
Or is it just a design still?
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