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Old 09 July 2017, 17:53   #1521
Black68
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Quote:
Originally Posted by 8 Bit Dreams View Post
Rev.3 is running on 48/50Mhz crystal, check this thread to find newest firmware


Nope, Rev.3 needs FPU to boot


Yes
Thanks for the answer.

If I want to run it at 25mhz I can use the firmware from the repository? (I have a 68030RC25 25Mhz).

EDIT: Nevermind, I just found the firmware files for different speed clocks.

Last edited by Black68; 09 July 2017 at 18:57.
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Old 09 July 2017, 19:29   #1522
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Quote:
Originally Posted by 8 Bit Dreams View Post
Rev.3 is running on 48/50Mhz crystal, check this thread to find newest firmware
Actually, the Rev 3 is still a 24Mhz clock with the regular CPLD. Steve has mentioned in one of his Videos that he uses a programmable crystal. When he had the TF530 up to 50Mhz, he had the CPLD's programmed to 50Mhz, as well as his Crystal / Oscillator programmed to 50Mhz.

You need a matching speed clock, to the speed the CPLD's have been compiled (and flashed) for.


Quote:
Nope, Rev.3 needs FPU to boot
Are you sure about that ?, the 68882 has NEVER been a system critical component. (Required for system to boot), Unless the CPLD has been coded to require it to boot. The board steve repaired on stream was a rev 2, but that booted without an FPU (Cause of the board not booting, dud 68881), and AFAIK the Rev 3 CPLD did not change that dramatically to require one at boot. The Eagle schematics do not hint the FPU is 100% necessary, so that leaves the CPLD, and without looking at the source jedec's, all the CPLD does is address translation for CS.

And Motorola certainly do not think it is system critical at boot to need one.

http://imgur.com/a/yYtUf

If I can be an arse for a second, my DKB Cobra (A1200), I can pull the 68882 from that, and the system will still boot. The 68030 could not care less if one was not present. (If the 68882 does not acknowledge its presence to the 68030, the 68030 doesn't crack the shits).

Steve can you clarify ?

Quote:
Yes
For now it still needs INT2, but that is what Steve was hinting about his work over this weekend, his changes to the CPLD *MAY* not require the INT2 now.
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Old 09 July 2017, 20:03   #1523
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not sure, however i have seen this, just follow the thread:
Quote:
Originally Posted by plasmab View Post
Cock! That beta may not work if the FPU is missing. Sorry!


Quote:
Originally Posted by plasmab View Post
My ROM needs an IDE drive plugged in. Just a bug in it I guess


Sent from my iPhone using Tapatalk
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Old 09 July 2017, 20:38   #1524
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Would it be possible to use 1Mbit x 8 RAM chips instead of the 512Kbit x 8 listed in the BOM file?
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Old 09 July 2017, 20:45   #1525
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Quote:
Originally Posted by Black68 View Post
Would it be possible to use 1Mbit x 8 RAM chips instead of the 512Kbit x 8 listed in the BOM file?
Yes, it is, but you need to find 5v chips, reroute the board and rewrite the firmware
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Old 09 July 2017, 21:55   #1526
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Quote:
Originally Posted by Black68 View Post
Would it be possible to use 1Mbit x 8 RAM chips instead of the 512Kbit x 8 listed in the BOM file?
I cannot find anyone who ever made 5V chips with the required pinout unfortunately. If you find some let me know and i'll write a firmware to use it. At the moment it will not use 4Mb of ram.

TBH stick to the BOM and watch the videos. Most of your questions have been answered.
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Old 09 July 2017, 21:59   #1527
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I'm very very close to completing the TF534S... I have added the address lines A31-A24 to the RAM CPLD which means the ram can potentially be plonked in Z3 space.
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Old 10 July 2017, 21:45   #1528
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just saw Your last vid ot the tube - both thumbs up!!!
please give me short answer about my early Rev.2 boards written in comments
Thank You!
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Old 10 July 2017, 22:53   #1529
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Just woken up to another notification flashing on my phone of another live video..., missed it... Something about living 10 or so hours ahead of the UK, and only like 3 hours behind the International Date Line.

Anyway.., yeah still waiting for boards..., I think you ordered them a week after me, and I am still waiting. I expect you might actually get yours first in Scotland, before me in Australia, incoming International mail likes to sit in customs for a month here in Australia, or they like only process a certain number each day, bugger the rest, lets go home boys...

Anyway, Liked... still waiting for boards to be delivered.
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Old 10 July 2017, 23:19   #1530
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Quote:
Originally Posted by 8 Bit Dreams View Post
just saw Your last vid ot the tube - both thumbs up!!!
please give me short answer about my early Rev.2 boards written in comments
Thank You!
Without going over the obvious, you have the right CPLD ? XC9532XL-VQ44

Secondly, The board needs to be in an A500, and powered, before it will program, because the CPLD's need voltages that the programmer cannot supply on its own.

This is based on the assumption that the CPLD and JTAG circuit is merely a copy / paste between TF520 / 530.
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Old 10 July 2017, 23:33   #1531
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Originally Posted by whiteb View Post
Without going over the obvious, you have the right CPLD ? XC9532XL-VQ44

Secondly, The board needs to be in an A500, and powered, before it will program, because the CPLD's need voltages that the programmer cannot supply on its own.

This is based on the assumption that the CPLD and JTAG circuit is merely a copy / paste between TF520 / 530.
Really!?
Are You sure???
Please watch last three minutes of the video:
[ Show youtube player ]
i see the plain board only...
however, i will try to plug them in A500, i just can't belive all three Xilinx bunches are fakes..
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Old 10 July 2017, 23:46   #1532
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Quote:
Originally Posted by 8 Bit Dreams View Post
Really!?
Are You sure???
Please watch last three minutes of the video:
[ Show youtube player ]
i see the plain board only...
however, i will try to plug them in A500, i just can't belive all three Xilinx bunches are fakes..
[edit] okay, from the eagle schematics, the chip is a 3.3V chip (Power and IO), which means the circuit must be powered so the Regulators can receive 5V, to drive the 3.3V lines..., and if the Xilinx forums are anything to go by, they need the source voltage applied to its power pins (3.3V in this case) in order to drive the Macrocell programming phase, regardless that the CPLD controller responds to a poll, the controller cannot apply programming to the macrocells without it receiving its base load power to the power pins (and respective ground available).

Steve to the rescue

I have 4 year old twins bouncing off the walls for breakfast, woman ordering stuff to do, and headphones crackly as all hell.

Anyway, in the TF530 repair video, he flashes the CPLD while he has Kickstart up on the stream. so the motherboard is powered.

Last edited by whiteb; 11 July 2017 at 00:17.
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Old 10 July 2017, 23:49   #1533
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why on Earth would you use resistor networks that small!!


I think I've ruined a board trying to get one of them soldered.
Which also means I've likely sacrificed all the HW already soldered to it.

GAH!!
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Old 11 July 2017, 00:38   #1534
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Originally Posted by Tachyon View Post
why on Earth would you use resistor networks that small!!


I think I've ruined a board trying to get one of them soldered.
Which also means I've likely sacrificed all the HW already soldered to it.

GAH!!
3.2mmx1.6mm ??.. hmmm still smaller than 0603 caps (I think), which is 6mmx3mm.

BLOODY LOTS OF FLUX time....., whats the pin space on a QFP208 ?, that was smegging fun I tell ya (Minimig FPGA). Flux, more flux, even more flux, and then add some flux.., oh and pre-solder the pads first worked for me, with even more lots of flux.

Anyway, my first rule is always do the small expendable shit before doing the expensive stuff. At least that was my motto with Minimig, Caps, resistors, regulators, then got the power circuit up and verified the voltages (Because it had external power), then on went the Ram, CPU and FPGA.

Anyway thanks for the tip..., Just upped my ResNet order from 3, to 30 pieces so I can practice on another board , drops the unit price from 15c down to 5c. I do not think I am game to order 100, to drop the unit price to 2c , waste of 50c

Last edited by whiteb; 11 July 2017 at 00:50.
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Old 11 July 2017, 00:59   #1535
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Roll eyes (sarcastic)

Quote:
Originally Posted by whiteb View Post
[edit] okay, from the eagle schematics, the chip is a 3.3V chip (Power and IO), which means the circuit must be powered so the Regulators can receive 5V, to drive the 3.3V lines..., and if the Xilinx forums are anything to go by, they need the source voltage applied to its power pins (3.3V in this case) in order to drive the Macrocell programming phase, regardless that the CPLD controller responds to a poll, the controller cannot apply programming to the macrocells without it receiving its base load power to the power pins (and respective ground available).

Steve to the rescue

I have 4 year old twins bouncing off the walls for breakfast, woman ordering stuff to do, and headphones crackly as all hell.

Anyway, in the TF530 repair video, he flashes the CPLD while he has Kickstart up on the stream. so the motherboard is powered.
hmm.. That's why we need J7 jumper, we are able to add +5v and gnd on it.. or it isn't enough po program the cpld?
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Old 11 July 2017, 01:19   #1536
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hmm.. That's why we need J7 jumper, we are able to add +5v and gnd on it.. or it isn't enough po program the cpld?
Well on the TF530 (according to Schematic / BRD eagle files), has an EXT5V header that directly feeds the Regulator to supply the 3.3V to the CPLD.

I do not know if the TF520 has that. (Dont have the files).
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Old 11 July 2017, 01:31   #1537
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Originally Posted by whiteb View Post
Well on the TF530 (according to Schematic / BRD eagle files), has an EXT5V header that directly feeds the Regulator to supply the 3.3V to the CPLD.

I do not know if the TF520 has that. (Dont have the files).
I do not know about TF520 too...still talking about TF530, but mine are from very early Rev.2 (Stephen has just uploaded the sources on Github, the link was not published yet) He also has written, that this rev is not tested yet, also TF symbol is missing on them, so i am in a doubt.. just want a confirmation of one of my theories:
It can be-
1. my progammer
2. Xilinx chips from three different sellers i've bought (even colour of print on the chips is different)
3. my shaking hands..
Just now You have added Nr. 4... I will try to program it in A500 tomorrow.. Will see does it makes any difference.
Quote:
Originally Posted by Tachyon View Post
why on Earth would you use resistor networks that small!!


I think I've ruined a board trying to get one of them soldered.
Which also means I've likely sacrificed all the HW already soldered to it.

GAH!!
are you trying to solder them with iron? don't do it! I have used a hot air station, it is very easy to do using it
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Old 11 July 2017, 01:56   #1538
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Just now You have added Nr. 4... I will try to program it in A500 tomorrow.. Will see does it makes any difference.
Well, going by what I can see of the datasheets, on boot, the controller checks for Jtag, if found, it then resets the CPLD, and puts the chip in to 'Config' mode ready for programming. But if the chip doesnt have its base power supply on its power and ground pins, it wont reboot in to config mode, for programming.

The Chips controller might respond..., but the main chip isnt. That is my take on it anyway.
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Old 11 July 2017, 02:42   #1539
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For those of you waiting to get boards from me... today I finally got the header delivery from China, except they sent the wrong ones!!!

2 months waiting for the damn thing and they send me the regular female pinstrips... Well luckily now I found a US seller which has them, so ordered from them, hopefully it won't be too long. I hate buying stuff from China.
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Old 11 July 2017, 03:40   #1540
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Dirty brown box from DirtyPCB's arrived

[edit] WOW, that's small......, I will have to rethink the soldering iron I use

Last edited by whiteb; 11 July 2017 at 03:55.
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